CY8C20x36/46/66, CY8C20396

Packaging Information

This section illustrates the packaging specifications for the CY8C20x36/46/66, CY8C20396 PSoC device, along with the thermal impedances for each package.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.

Figure 14. 16-Pin Chip On Lead 3x3 mm (Sawn)

001-09116 *D

Figure 15. 24-Pin (4x4 x 0.6 mm) QFN

001-13937 *B

Document Number: 001-12696 Rev. *D

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Cypress CY8C20x36, CY8C20x46, CY8C20396, CY8C20x66 manual Packaging Information, Pin Chip On Lead 3x3 mm Sawn