Cypress CY8C24123A AC Low Power Comparator Specifications, AC Digital Block Specifications, Spim

CY8C24123A

CY8C24223A, CY8C24423A

AC Low Power Comparator Specifications

Table 38 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 38. AC Low Power Comparator Specifications

Symbol	Description	Min	Typ	Max	Units	Notes
TRLPC	LPC response time	–	–	50	μs	≥ 50 mV overdrive comparator
						reference set within VREFLPC

AC Digital Block Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 39. 5V and 3.3V AC Digital Block Specifications

Function	Description	Min	Typ	Max	Units	Notes
Timer	Capture Pulse Width	50a	–	–	ns
	Maximum Frequency, No Capture	–	–	49.2	MHz	4.75V < Vdd < 5.25V
	Maximum Frequency, With Capture	–	–	24.6	MHz
Counter	Enable Pulse Width	50a	–	–	ns
	Maximum Frequency, No Enable Input	–	–	49.2	MHz	4.75V < Vdd < 5.25V
	Maximum Frequency, Enable Input	–	–	24.6	MHz
Dead Band	Kill Pulse Width:
	Asynchronous Restart Mode	20	–	–	ns
	Synchronous Restart Mode	50a	–	–	ns
	Disable Mode	50a	–	–	ns
	Maximum Frequency	–	–	49.2	MHz	4.75V < Vdd < 5.25V
CRCPRS	Maximum Input Clock Frequency	–	–	49.2	MHz	4.75V < Vdd < 5.25V
(PRS Mode)
CRCPRS	Maximum Input Clock Frequency	–	–	24.6	MHz
(CRC Mode)
SPIM	Maximum Input Clock Frequency	–	–	8.2	MHz	Maximum data rate at 4.1 MHz
						due to 2 x over clocking.
SPIS	Maximum Input Clock Frequency	–	–	4.1	ns
	Width of SS_ Negated Between Transmissions	50a	–	–	ns
Transmitter	Maximum Input Clock Frequency	–	–	24.6	MHz	Maximum data rate at 3.08
						MHz due to 8 x over clocking.
	Maximum Input Clock Frequency with Vdd ≥	–	–	49.2	MHz	Maximum data rate at 6.15
	4.75V, 2 Stop Bits					MHz due to 8 x over clocking.
Receiver	Maximum Input Clock Frequency	–	–	24.6	MHz	Maximum data rate at 3.08
						MHz due to 8 x over clocking.
	Maximum Input Clock Frequency with Vdd ≥	–	–	49.2	MHz	Maximum data rate at 6.15
	4.75V, 2 Stop Bits					MHz due to 8 x over clocking.

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

Document Number: 38-12028 Rev. *I Page 39 of 56

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