CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *I Page 13 of 56
34 IO P1[6]
35 IO P5[0]
36 IO P5[2]
37 IO P3[0]
38 IO P3[2]
39 IO P3[4]
40 IO P3[6]
41 Input XRES Active high external reset with
internal pull down.
42 OCD HCLK OCD high-speed clock output.
43 OCD CCLK OCD CPU clock output.
44 IO P4[0]
45 IO P4[2]
46 IO P4[4]
47 IO P4[6]
48 IO I P2[0] Direct switched capacitor block
input.
49 IO I P2[2] Direct switched capacitor block
input.
50 IO P2[4] External Analog Ground (AGND).
51 IO P2[6] External Voltage Reference
(VRef).
52 IO I P0[0] Analog column mux input.
53 IO I P0[2] Analog column mux input and
column output.
54 IO I P0[4] Analog column mux input and
column output.
55 IO I P0[6] Analog column mux input.
56 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.
Table 7. Pin Definitions - 56-Pin SSOP (continued)
Pin
No. Type Pin
Name Description
Digital Analog
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