Cypress CY8C24123A manual AC External Clock Specifications

CY8C24123A

CY8C24223A, CY8C24423A

Table 43. 2.7V AC Analog Output Buffer Specifications

Symbol	Description	Min	Typ	Max	Units
TROB	Rising Settling Time to 0.1%, 1V Step, 100 pF Load	–	–	4	μs
	Power = Low
	Power = High	–	–	4	μs
TSOB	Falling Settling Time to 0.1%, 1V Step, 100 pF Load	–	–	3	μs
	Power = Low
	Power = High	–	–	3	μs
SRROB	Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load	0.4	–	–	V/μs
	Power = Low
	Power = High	0.4	–	–	V/μs
SRFOB	Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load	0.4	–	–	V/μs
	Power = Low
	Power = High	0.4	–	–	V/μs
BWOB	Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load	0.6	–	–	MHz
	Power = Low
	Power = High	0.6	–	–	MHz
BWOB	Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load	180	–	–	kHz
	Power = Low
	Power = High	180	–	–	kHz

AC External Clock Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 44. 5V AC External Clock Specifications

Symbol	Description	Min	Typ	Max	Units
FOSCEXT	Frequency	0.093	–	24.6	MHz
–	High Period	20.6	–	5300	ns
–	Low Period	20.6	–	–	ns
–	Power Up IMO to Switch	150	–	–	μs
Table 45. 3.3V AC External Clock Specifications
Symbol	Description	Min	Typ	Max	Units
FOSCEXT	Frequency with CPU Clock divide by 1a	0.093	–	12.3	MHz
FOSCEXT	Frequency with CPU Clock divide by 2 or greaterb	0.186	–	24.6	MHz
–	High Period with CPU Clock divide by 1	41.7	–	5300	ns
–	Low Period with CPU Clock divide by 1	41.7	–	–	ns
–	Power Up IMO to Switch	150	–	–	μs

a.Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

b.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met.

Document Number: 38-12028 Rev. *I Page 42 of 56

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