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CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *I Page 27 of 56
Figure 13. Basic Switch Mode Pump Circuit
ΔVPUMP_Line Line Regulation (over VBAT range) – 5 – %VO Configuration listed in footnote.a
VO is the “Vdd Value for PUMP
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
Specification, Table 29 on page 30.
ΔVPUMP_Load Load Regulation – 5 – %VO Configuration listed in footnote.a
VO is the “Vdd Value for PUMP
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
Specification, Table 29 on page 30.
ΔVPUMP_Ripple Output Voltage Ripple (depends on
capacitor/load) – 100 – mVpp Configuration listed in footnote.a
Load is 5 mA.
E3Efficiency 35 50 – % Configuration listed in footnote.a
Load is 5 mA. SMP trip voltage is
set to 3.25V.
E2Efficiency
FPUMP Switching Frequency – 1.3 – MHz
DCPUMP Switching Duty Cycle – 50 – %
a. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure13.
Table 24. DC Switch Mode Pump (SMP) Specifications (continued)
Symbol Description Min Typ Max Units Notes
Battery C1
D1
+PSoCVdd
Vss
SMP
VBAT
L1
VPUMP
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