CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *I Page 40 of 56
Table 40. 2.7V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
Functions Maximum Block Clocking Frequency 12.7 MHz 2.4V < Vdd < 3.0V
Timer Capture Pulse Width 100a–0–0ns
Maximum Frequency, With or Without Capture – – 12.7 MHz
Counter Enable Pulse Width 100a–0–0ns
Maximum Frequency, No Enable Input – – 12.7 MHz
Maximum Frequency, Enable Input – – 12.7 MHz
Dead
Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 100a–0–0ns
Disable Mode0100a–0–0ns
Maximum Frequency – – 12.7 MHz
CRCPRS
(PRS
Mode)
Maximum Input Clock Frequency – – 12.7 MHz
CRCPRS
(CRC
Mode)
Maximum Input Clock Frequency – – 12.7 MHz
SPIM Maximum Input Clock Frequency – – 6.35 MHz Maximum data rate at 3.17 MHz
due to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.23 ns
Width of SS_ Negated Between Transmissions 100a–0–0ns
Trans-
mitter Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz
due to 8 x over clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
[+] Feedback