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CY8C24123A
- page 48
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56
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56 pages, 1.41 Mb
CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *I
Page 48 of 56
Figure 28. 28-Pin (300-Mil) Molded DIP
Figure 29. 28-Pin (210-Mil) SSOP
51-85014 *D
51-85079 *C
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Contents
Main
CY8C24123A
PSoC Programmable System-on-Chip
Features
Logic Block Diagram
CY8C24123A CY8C24223A, CY8C24423A
PSoC Functional Overview
PSoC Core
Digital System
CY8C24123A CY8C24223A, CY8C24423A
Analog System
CY8C24123A CY8C24223A, CY8C24423A
Additional System Resources
PSoC Device Characteristics
Getting Started
Development Kits
Development Tools
PSoC Designer Software Subsystems
PSoC Designer Core Engine
PSoC Designer
Hardware Tools
Designing with User Modules
Application Editor
Debugger
Device Editor
Document Conventions
Acronyms Used
Units of Measure
Numeric Naming
CY8C24123A CY8C24223A, CY8C24423A
Pinouts
8-Pin Part Pinoutt
PDIP SOIC
20-Pin Part Pinout
PDIP SSOP SOIC
28-Pin Part Pinout
PDIP SSOP SOIC
32-Pin Part Pinout
CY8C24123A
56-Pin Part Pinout
Page
Register Reference
Register Conventions
Register Mapping Tables
Table 9. Register Map Bank 0 Table: User Space
Table 9. Register Map Bank 0 Table: User Space (continued)
Table 10. Register Map Bank 1 Table: Configuration Space
Table 10. Register Map Bank 1 Table: Configuration Space (continued)
Electrical Specifications
Absolute Maximum Ratings
Operating Temperature
DC Electrical Characteristics
Page
CY8C24223A, CY8C24423A
Page
CY8C24123A CY8C24223A, CY8C24423A
Page
Page
+PSoC
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Page
Page
Page
AC Electrical Characteristics
Page
Figure 14. PLL Lock Timing Diagram
Figure 15. PLL Lock for Low Gain Setting Timing Diagram
Figure 16. External Crystal Oscillator Startup Timing Diagram
Figure 17. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 18. 32 kHz Period Jitter (ECO) Timing Diagram
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Page
Page
0 0.01 0.1 1.0 10
Page
Page
CY8C24123A
Page
Page
CY8C24223A, CY8C24423A
SDA SCL SSr SP
T
T T T T
T
Packaging Information
Packaging Dimensions
Figure 23. 8-Pin (300-Mil) PDIP
DIMENSIONS IN INCHES MIN. MAX.
51-85075 *A
Figure 24. 8-Pin (150-Mil) SOIC
Figure 25. 20-Pin (300-Mil) Molded DIP
51-85011-A
51-85066 *C
20-Lead(300-Mil) Molded DIP P5
Page
Page
Figure 30. 28-Pin (300-Mil) Molded SOIC
Figure 31. 32-Pin (5x5 mm) QFN
EXPOSED
PAD
LF32
Page
Thermal Impedances Capacitance on Crystal Pins
Solder Reflow Peak Temperature
Development Tool Selection
Software
Development Kits
Evaluation Tools
Device Programmers
Accessories (Emulation and Programming)
Third Party Tools
Build a PSoC Emulator into Your Board
Ordering Information
Ordering Code Definitions
CY 8 C 24 xxx-SPxx
Document History Page
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Products
PSoC Solutions