Epson SEIJ98006 manual Combined reset circuit + timer circuit, 12. Reset/timer combined circuit

EPSON Stylus Color 900 Revision C

The control circuits are explained in detail below.

[Combined (reset circuit + timer) circuit]

A combined circuit RTC9810 manages both reset signal production and RTC (Rear Time Controller). It produces reset signals by monitoring the both 5 VDC line (input to Pin 7) and 42 VDC line (input to Pin 9). When the voltage level for the 5 VDC line drops to 4.3 V, or the voltage level for the 42 VDC line drops to 35.5 V, the combined circuit outputs a reset signal from Pin 2. When the printer is turned on / off or detects abnormal voltage level, the IC sends the reset signal to the following ICs to avoid printer damage caused by run-away of the logic line and abnormal operation of driver systems. Also, to let the motor driver IC execute its

job properly, the reset signal is once input to the convertor (setting current production IC) on the main board to stop motors in the correct sequence.

On the other hand, the timer control is done by counting the operation of the oscillator circuit, and the printer’s power off time can be confirmed based on the timer at the next power on operation. Also, this count data is used to manage the timer for the operation such as periodical flashing during power on time as well as power off time.

While the printer is on, the printer supplies 5 V (input to Pin 7) to operate the internal oscillation circuit, however, when the printer is turned off, the external button-cell battery (a lithium battery) immediately starts supplying voltage (3 V) to the Pin 8.

R 1 8

1 0 7

K

9 V

+ 4 2

V

D r o p s t o 3 5

V I N

+ 5

V

7 V D D

D e v is io n

B A T 1

8 R T C 9 8 1 0 ( I C 8 )

R 2 0 1 0 K

S p e e d

V B K

u p

V

3 . 0

d io d e

1 4

G N DR/ AD CS C

S

2

4

E

5

6

T

L

8 1

4 3

T

A

K

3 62 27 62 5

/ R S

/ R S

/ R S

T D A

T C L

T C E

H D 6 4 F 2 3 5 7E(0I C5 B1 )5 9 ( I E 0 5 B 6 0 ( I C 3 )

T

T

T

T

K

A

M 6 2 3 8

3 ( I C 1 7

) 2

V R E F 1

4 7 ( I C 1 1 )

3

1

3

L B 1 8

1

2

D /

A x x

V R E F 2

A8x y

2

/ R S T D /

V R E F 1

3

R E AF

3 9 5

7 ( I C 1 3 )

4

1

L B 1 8

4

7 ( I

D /

A y x

V R E F 2

3

R E AF 3 9 5

7 ( I C 1 4 )

Figure 2-12. Reset/timer combined circuit

Operating Principles Electrical Circuit Operation Principles 61