Intel 8080 manual Min. Max. Unit Test Condition, Typical ~ Output Delay VS. ~ Capacitance

SILICON GATE MOS 8080A-2

A.C. CHARACTERISTICS (Continued)

TA = O°C to 70°C, VOD = +12V ± 5%, Vee = +5V ± 5%, VBB = -5V ± 5%, Vss = OV, Unless Otherwise Noted

Symbol

tOS2

toH [1]

tiE [2]

tRS

tHS

tiS

tH

tFD tAW [2] tow [2] tWD[2] tWA [2]

Parameter

Data Setup Time to <P2 During DBIN Data Hold Time From </>2 During DBIN INTE Output Delay From <P2 READY Setup Time During <P2 HOLD Setup Time to ep2

INT Setup Time During cfJ2 (During <1>1 in Halt Mode) Hold Time From ep2 (READY, INT, HOLD)

Delay to Float During Hold (Address and Data Bus) Address Stable Prior to WR

Output Data Stable Prior to WR

Output Data Stable From WR

Address Stable From WR

Min. Max. Unit Test Condition

130nsec

[1]nsec

200 nsec CL = 50pf

90nsec

120nsec

100nsec

0nsec

120 nsec

[5]nsec -

[6]nsec

[7]nsec

[7]nsec - CL = 100pf: Address, Data

--

CL=50pf: WR, HLDA, DBIN

t/),

tHF[2]	HLDA to Float Delay	[8]	nsec
tWF[2]	WR to Float Delay	[9]	nsec
tAH[2]	Address Hold Time After DBIN During HLDA	-20	nsec	-

NOTES:

1.Data input should be enabled with DBIN status. No bus conflict can then occur and data hold time is assured. tOH = 50 ns or tOF. whichever is less.

2.Load Circuit.

+5V

2.1K

8080A OUTPUT

A'S-AO

07 -00

SYNC

DBIN

WR

READY

WAIT

HOLD

HLDA

INT

INTE

to-

tWA

,.-

two

toc

I -

-... t oc . -

I

3. tCY =t03 + t r4>2 + t4>2 + tf4>2 + t02 + t r4>1 ~ 380ns.

TYPICAL ~ OUTPUT DELAY VS. ~ CAPACITANCE

+20, .... ---- ..... ------- , ------ y ------ .

.=.

> +10

«

-J

w

0

t- O

:::>

Q..

t-

:::> -100

<1

-50o +50+100

~CAPACITANCE (pf)

(CACTUAL - CSPEC )

4.The following are relevant when interfacing the 8080A to devices having V,H = 3.3V:

a)Maximum output rise time from .8V to 3.3V = 100ns @ CL = SPEC.

b)Output delay when measured to 3.0V = SPEC +60ns @ CL = SPEC.

c)If CL #: SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL < CSPEC.

5. tAW = 2 tCY -t03 -tr</>2 -130nsec. .

6.tow = tCY -t03 -tr4>2 -170n5ec.

7.If not HLOA, two =twA = tD3 + t r</>2 +10n5. If HLDA, two =twA = tWF.

8.t HF = t03 + t r4>2 -SOns.

9.twF = t03 + t rcf)2 -10ns

10.Data in must be stable for this period during DBIN °T3. Both tOS1 and tOS2 must be satisfied.

11.Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.)

12.Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3, T4, T5 and TWH when in hold mode. (External synchronization is not required.)

13.Interrupt signal must be uable during this period of the last clock cycle of any instruction in order to be recognized on the followi,1g instruction. (External synchronization is not required.)

14.This timing diagram shows timing relationships only; it does not represent any s~ific machine cycle.

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