NOTES:

1.The first memory cycle (M 1) is always an instruction fetch; the first (or only) byte, containing the op code, is fetched during this cycle.

2.If the READY input from memory is not high during T2 of each memory cycle, the processor will enter a wait state (TW) until READY is sampled as high.

3.States T 4 and T5 are present, as required, for opera- tions which are completely internal to the CPU. The con- tents of the internal bus during T4 and T5 are available at the data bus; this is designed for testing purposes only. An "X" denotes that the state is present, but is only used for such internal operations as instruction decoding.

4.Only register pairs rp = B (registers B and C) or rp = D (registers D and E) may be specified.

5.These states are ski pped.

6.Memory read sub-cycles; an instruction or data word will be read.

7.Memory write sub-cycle.

8.The READY signal is not required during the second and third sub-cycles (M2 and M3). The HOLD signal is accepted during M2 and M3. The SYNC signal is not gene- rated during M2 and M3. During the execution of DAD,

M2 and M3 are required for an internal register-pair add; memory is not referenced.

9.The results of these arithmetic, logical or rotate in- structions are not moved into the accumulator (A) until state T2 of the next instruction cycle. That is, A is loaded while the next instruction is being fetched; this overlapping of operations allows for faster processing.

10.If the value of the least significant 4-bits of the accumu- lator is greater than 9 or if the auxjliary carry bit is set, 6 is added to the accumulator. If the value of the most signifi- cant 4-bits of the accumulator is now greater than 9, ~ if the carry bit is set, 6 is added to the most significant 4-bits of the accumulator.

11.This represents the first sub-cycle (the instruction fetch) of the next instruction cycle.

12.If the condition was met, the contents of the register

pair WZ are output on the address lines (Ao-1S) instead of the contents of the program counter (PC).

13.If the condition was not met, sub-cycles M4 and M5 are skipped; the processor instead proceeds immediately to the instruction fetch (Ml) of the next instruction cycle.

14.If the condition was not met, sub-cycles M2 and M3 are skipped; the processor instead proceeds immediately to the instruction fetch (M 1) of the next instruction cycle.

15.Stack read sub-cycle.

16.Stack write sub-cycle.

17. CONDITION

CCC

NZ

-

not zero (Z = 0)

000

Z

-

zero (Z = 1)

001

NC

-

no carry (CY = 0)

010

C

-

carry (CY = 1)

011

PO

 

parity odd (P=O)

100

PE

 

parity even (P = 1)

101

P

 

plus (S= 0)

110

M

 

minus (S = 1)

111

18.I/O sub-cycle: the I/O port's 8-bit select code is dupli- cated on address lines 0-7 (Ao-7) and 8-15 (AS-1S).

19.Output sub-cycle.

20.The processor will remain idle in the halt state until an interrupt, a reset or a hold is accepted. When a hold re- quest is accepted, the CPU enters the hold mode; after the hold mode is terminated, the processor returns to the halt state. After a reset is accepted, the processor begins execu- tion at memory location zero. After an interrupt is accepted, the processor executes the instruction forced onto the data bus (usually a restart instruction).

SSS or DDD

Value

rp

Value

A

111

B

00

B

000

D

01

C

001

H

10

D

010

SP

11

E

011

 

 

H

100

 

 

L

101

 

 

2-20

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Image 34
Intel 8080 manual Value, 111 000 001 010 011 100 101

8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.