Intel 8080 manual Instruction SET

INSTRUCTION SET

Summary of Processor Instructions

		try		Instruction Code [11							Clock 121
Mnemonic	Description		06	Os	04 03 02 0, DO						Cycles
MOV r1 ,r2	Move register to register	0	1	0	0 0 S S S						5
MOVM,r	Move register to memory	0	1	1	1	0	S		S	S	7
MOVr,M	Move memory to register	0	1	0	0	0	1	1 0			7
HlT	Halt	0	1	1	1	0	1	1 0			7
MVI r	Move immediate register	0	0	0	0 0 1 1 0						7
MVIM	Move immediate memory	0	0	1	1	0	1		1	0	10
INR r	Increment register	0	0	0	0 0 1 0 0						5
OCR r	Decrement register	0	0	0	0	0	1	0 1			5
INR M	Increment memory	0	0	1	1	0	1		0	0	10
OCR M	Decrement memory	0	0	1	1	0	1		0	1	10
ADOr	Add register to A	1	0	0	0	0	S	S S			4
AOCr	Add register to A with carry	1	0	0	0	1	S		S	S	4
SUB r	Subtract register from A	1	0	0	1	0	S		S	S	4
SBB r	Subtract register from A	1	0	0	1	1	S		S	S	4
	with borrow
ANA r	And register with A		0				S		S	S	4
XRA r	Exclusive Or register with A		0				S		S	S	4
OIiAr	Or register with A		0				S		S	S	4
CMPr	Compare register with A		0				S		S	S	4
ADD M	Add memory to A		0				1		1	0	7
AOC M	Add memory to A with carry		0				1		1	0	7
SUB M	Subtract memory from A		0				1		1	0	7
SBB M	Subtract memory from A		0				1		1	0	7
	with borrow
ANA M	And memory with A		0		0	0
XRA M	Exclusive Or memory with A		0		0	1
ORA M	Or memory with A		0		1	0
CMPM	Compare memory with A		0		1 1
AOI	Add immediate to A		1		0	0
ACI	Add immediate to A with		1		0	1
	carry
SUI	Subtract immediate from A
SBI	Subtract immediate from A
	with borrow
ANI	And immediate with A
XRI	Exclusive Or immediate with
ORI	A
	Or immediate with A	1				0
CPI	Compare immediate with A	1				1
RLC	Rotate A left	0				0
RRC	Rotate A right	0				1
RAl	Rotate A left through carry	0				0
RAR	Rotate A right through	0				1
	carry
JMP	Jump unconditional			0	0	0	0		1	1	10
JC	Jump on carry			0	1 1		0		1	0	10
JNC	Jump on no carry			0	1 0		0		1	0	10
JZ	Jump on zero			0	0	1	0		1	0	10
JNZ	Jump on no zero			0	0	0	0		1	0	10
JP	Jump on positive			1	1 0		0	1 0			10
JM	Jump on minus			1	1 1		0	1 0			10
JPE	Jump on parity even			1	0	1	0		1	0	10
JPO	Jump on parity odd			1	0	0	0		1	0	10
CALL	Call unconditional			0	0	1	1		0	1	17
CC	Call on carry			0	1 1 1 0 0						11/17
CNC	Call on no carry			0	1 0 1 0 0						11/17
CZ	Call on zero			0	0	1	1		0	0	11/17
CNZ	Call 0 n no zero			0	0	0	1		0	0	11/17
CP	Call on positive			1	1 0 1 0 0						11/17
CM	Call on minus			1	1 1 1 0 0						11/17
CPE	Call on parity even			1	0 1 1 0 0						11/17
CPO	Call on parity odd			1	0	0	1		0	0	11/17
RET	Return			0	0	1	0	0 1			10
RC	Return on carry			0	1 1 0 0 0						5/11
RNC	Return on no carry			0	1	0	0		0	0	5/11

Mnemonic

RZ

RNZ

RP

RM

RPE

RPO

RST IN OUT lXI B

LXI 0

LXI H

lXI SP PUSH B

PUSH 0

PUSH H

PUSH PSW

POP B

POP 0

POP H

POP PSW

STA lOA

XCHG

XTHl

SPHL

PCHL

DAD B DAD 0 DAD H DAD SP STAX B STAX 0 LOAX B lOAX 0

INX B

INX 0

INX H

INX SP DCX B DCX 0 DCX H DCX SP CMA STC CMC OAA SHlD

LHLO EI

01 NOP

			Instruction Code [11								Clock [21
Description	07	06	Os		04		03	02	0,	DO	Cycles
Return on zero	1		0		0		'1	0	0	0	5/11
Return on no zero	1		0		0		0	0	C	0	5/11
Return on positive	1		1		1		0	0	0	0	5/11
Return on minus	1		1		1		1	0	0	0	5/11
Return on parity even	1		1 0 1 0 0 0								5/11
Return on parity odd	1		1		0		0	0	0	0	5/11
Restart	1		A A A 1 1 1								11
Input	1		0		1		1	0	1	1	10
Output	1		0		1		0	0	1	1	10
load Immediate register	0		0		0		0	0	0	1	10
Pair B & C
Load immediate register											10
Pair 0 & E
Load immediate register											10
Pair H & L
load immediate stack pointer											10
Push register Pair B & C on											11
stack
Push register Pair 0 & E on											11
stack
Push register Pair H & l on											11
stack
Push A and Flags											11
on stack
Pop register pair B & C off											10
stack
Pop register pair 0 & E off											10
stack
Pop register pair H & L off											10
stack
Pop A and Flags											10
off stack
Store A direct											13
Load A direct											13
Exchange 0 & E, H& L											4
Registers
Exchange top of stack, H& l	1	1	1		0		0	0	1	1	18
H & L to stack pointer	1	1	1		1		1	0	0	1	5
H & L to program counter	1	1	1		0		1	0	0	1	5
Add B & C to H & L	0	0	0		0		1	0	0	1	10
Add 0 & E to H & L	l:'	0	0		1		1	0	0	1	10
Add H & L to H & L	0	0	1		0		1	0	0	1	10
Add stack pointer to H & L	0	0	1		1		1	0	0	1	10
Store A indirect	0	0	0		0		0	0	1	0	7
Store A indirect	0	0	0		1		0	0	1	0	7
load A indirect	0	0	0		0		1	0	1	0	7
Load A indirect	0	0	0		1		1	0	1	0	7
Increment B & C registers	0	0	0		0		0	0	1	1	5
Increment 0 & E registers	0	0	0		1		0	0	1	1	5
Increment H & L registers	0	0	1	0		0 0 1 1					5
Increment stack pointer	0	0	1		1		0	0	1	1	5
Decrement B & C	0	0	0		0		1	0	1	1	5
Decrement 0 & E	0	0	0		1		1	0	1	1	5
Decrement H & L	0	0	1		0		1	0	1	1	5
Decrement stack pointer	0	0	1		1		1	0	1	1	5
Complement A	0	0	1		0		1	1 1 1			4
Set carry	0	0	1		1		0	1	1	1	4
Complement carry	0	0	1		1		1	1	1	1	4
Decimal adjust A	0	0	1 0 0 1 1 1								4
Store H & l direct	0	0	1	0		0 0 1 0					16
load H & L direct	0	0	1		0		1	0	1	0	16
Enable Interrupts	1	1	1		1		1	0	1	1	4
Disable interrupt	1	1	1		1		0	0	1	1	4
No-operation	0	0	0		0		0	0	0	0	4

NOTES: 1. DDD or SSS - 000 B - 001 C - 010 D - 011 E - 100 H - 101 L - 110 Memory - 111 A. 2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags.

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