Intel 8080 manual Absolute Maximum Ratings, IOL = 1.9mA on all outputs, Operation

Models: 8080

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SILICON GATE MOS M8080A

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias

-55°C to +125°C

Storage T emperatu re

_65°C to + 150°C

All Input or Output Voltages

 

With Respect to VBB

-0.3V to +20V

Vcc, Voo and Vss With Respect to VBB

-0.3V to +20V

Power Dissipation

. . . . . . .. 1.7W

*COMMENT: Stresses above those listed under "Absolute Maxi- mum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the de- vice at these or any other conditions above those indicated in the operational sections of this specification is not implied. Ex- posure to absolute maximum rating conditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS

TA = -55°C to +125°C, VOD = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted.

Symbol

Parameter

Min.

Typ.

Max.

VILC

Clock Input Low Voltage

Vss-l

 

Vss+0.8

VIHC

Clock Input High Voltage

8.5

 

Voo+1

VIL

Input Low Voltage

Vss-l

 

Vss +0.8

VIH

Input High Voltage

3.0

 

Vcc+1

VOL

Output Low Voltage

 

 

0.45

VO H

Output High Voltage

3.7

 

 

IOD(AV)

Avg. Power Supply Current (Voo )

 

50

80

ICC (AV)

Avg. Power Supply Current (Vec)

 

60

100

IBB(AV)

Avg. Power Supply Current (VBB )

 

.01

1

IlL

Input Leakage

 

 

±10

ICL

Clock Leakage

 

 

±10

IDL [2]

Data Bus Leakage in Input Mode

 

 

-100

 

 

 

 

-2.0

IFL

Address and Data Bus Leakage

 

 

+10

During HOLD

 

 

-100

 

 

 

Unit

V

V

V

V

V

V rnA mA mA J1A J1A

J1A rnA

J1A

Test Condition

}IOL = 1.9mA on all outputs,

IOH = 150J-lA.

} Operation

TCy = .48 J.1.sec

Vss ~ VIN ~ Vcc

Vss ~ VCLOCK ~ VDD

VSS ~VIN ~VSS +O.~V

VSS +0.8V ~VIN ~VCC

VADDR/DATA = VCC VADDR/DATA = Vss + O.45V

CAPACITANCE

TA = 25°C

Vec = VOD = Vss = OV, VBB =-5V

 

Symbol

Parameter

Typ.

Max.

Unit

Clock Capacitance

17

25

pf

CIN

Input Capacitance

6

10

pf

CO UT

Output Capacitance

10

20

pf

NOTES:

 

 

 

 

1.The RESET signal must be active for a minimum of 3 clock cycles.

2.When DBIN is high and VIN > VIH an internal active pull up will be switched onto the Oata Bus.

3.~I supply / ~TA = -0.45%/C.

Test Condition

fc = 1 MHz

Unmeasured Pins

Returned to Vss

I-

2

~

a:

:::>

u

>

...J

8:

:::>

en

TYPICAL SUPPLY CURRENT VS. TEMPERATURE, NORMALIZEO.l3]

1 . 5, ..... ------ r ----------- ,

1.0J---------:::::l~I------______I

0.5t ------ J ------- ______ I

-55+50+125

AMBIENT TEMPERATURE rc)

DATA BUS CHARACTERISTIC

DURING DBIN

MAX

°0"----------------------

30--

Vee

Page 95
Image 95
Intel 8080 manual Absolute Maximum Ratings, IOL = 1.9mA on all outputs, Operation