Intel 8080 manual ClK 0.......-..-.-----.. tf1A TTL, ~50ns, High Level Driver Design

OSCILLATOR

			20MHz
	330		330
	~		~""""--01>-......------------.......--------.... OSC
	74S04				CLOCK GENERATOR
					7486
			DB	OB
				74163
			DC OC ....... -- ... ------- '
					7486
			GND--+-~
						10 -- + ---------.. 4>2 (TTL)
						AUXILIARY FUNCTIONS
						r ----- IIIIII ---- SYNC
				74HOO
						'----........--410
			WAVEFORMS			74S74
						ClK 0.......-..-.-----.. tf>1A (TTL)
	----u		u
4>1
	---f 1~~~	~50ns		'~__-Ir-		WA IT REO ------ 41 --- 1 0 a	READY
4>2	-- '	\	250ns ,			74574
50ns~ t+- --.f			r- 50ns			ClK
					I
4>1A	---I		, 250ns ,	,
SYNC			---1'	\		DMAREO--~----IID a	HOLD
						74S74

,\,.-_---1'ClK

Figure 3-3. 8080 Clock Generator

20 MHZ oscillator, a four bit counter, and gating circuits.

The oscillator provides a 20 MHZ signal to the input of a four (4) bit, presettable, synchronous, binary counter. By presetting the counter as shown in figure 3-3and clocking it with the 20 MHZ signal, a simple decoding of the counters outputs using standard TTL gates, provides proper timing for the two (2) 8080 clock inputs.

Note that the timing must actually be measured at the output of the High Level Driver to take into ac- count the added delays and waveform distortions within such a device.

positive transition when biased from the 8080 Voo supply (12V) but to achieve the low voltage specifi-

cation (VILC ) .8 volts Max. the driver is biased to the 8080 Vss supply (-5V).This allows the driver to

swing from GND to Vo o with the aid of a simple resistor divider.

Alow resistance series network is added between the driver and the 8080 to eliminate any overshoot of the pulsed waveforms. Now a circuit is apparent that can easily comply with the 8080 specifications. In fact rise and falltimes of this design are typically less than 10 ns.

+12V

High Level Driver Design

The voltage level of the clocks for the 8080 is not TTL compatible like the other signals that input to the 8080. The voltage swing is from .6 volts (VILC ) to 11 volts (VIHC ) with risetimes and falltimes under 50 ns. The Capacitive Drive is 20 pf (max.). Thus, a High Level Driver is required to interface the outputs of the Clock Generator (TTL) to the 8080.

The two (2) outputs of the Clock Generator are ca- pacitivity coupled to a dual- High Level clock driver. The driver must be capable of complying with the 8080 clock input specifications, page 5-15. A driver of this type usually has little problem supplying the

	6
6S0pF			47n	cf>1
cf>1 (TTL) ---1	2
	MH0026			(SOSO PIN 22)
680 pF	OR		47n
	EQUIV.	5		¢2
¢2 (TTL)-)
	4			(8080 PIN 15)
	3
		15K	15K

.68 J.LF

100n

-5V

Figure 3-4. High Level Driver

3-3