10 -------- ... --- MEMR TO

MEMORY

r> ----- . --- + ---- MEMW } DEVICES

SYSTEM

CONTROL

(8228)

I/OR} NOT

I/O R (MMJ-

_

USED

TO I/O

IIOW

 

DEVICES

 

 

I/OW (MM)

The second example uses Memory Mapped I/O and linear select to show how thirteen devices (8255) can be ad- dressed without the use of extra decoders. The format shown could be the second and third bytes of the LDA or STA in- structions or any other instructions used to manipulate I/O using the Memory Mapped technique.

It is easy to see that such a flexible I/O structure, that can be "tailored" to the overall system environment, provides the designer with a powerful tool to optimize efficiency and minimize component count.

Figure 3-10. Memory Mapped I/O.

I/O Addressing

With both systems of I/O structure the addressing of each device can be configured to optimize efficiency and re- duce component count. One method, the most common, is to decode the address bus into exclusive "chip selects" that enable the addressed I/O device, similar to generating chip- selects in memory arrays.

Another method is called "Iinear select". In this method, instead of decoding the Address Bus, a singular bit from the bus is assigned as the exclusive enable for a specific I/0 de- vice. This method, of course, limits the number of I/O de- vices that can be addressed but eliminates the need for extra decoders, an important consideration in small system design.

A simple example illustrates the power of such a flexi- ble I/O structure. The first example illustrates the format of the second byte of the IN or 0 UT instruction usi ng the Iso- lated I/O technique. The devices used are Intel®8255 Pro- grammable Peripheral Interface units and are linear selected. Each device has three ports and from the format it can be seen that six devices can be addressed without additional de- coders.

EXAMPLE #1

 

}

PORT SELECTS

' --

}

DEVICE SELECTS

ADDRESSES - 6 - 82555

(18 PORTS -144 BITS)

Figure 3-11. Isolated I/O - (Linear Select) (8255)

EXAMPLE #2

 

}

PORT SELECTS

' --

}

DEVICE SELECTS

DEVICE SELECTS

"' ------------1/0FLAG I =I/O

0= MEMORY

ADDRESSES -13 - 82555 (39 PORTS - 312 BITS)

Figure 3-12. Memory Mapped I/O - (Linear Select (8255)

I/O Interface Example

In Figure 3-16 a typical I/O system is shown that uses a variety of devices (8212, 8251 and 8255). It could be used to interface the peripherals around an intelligent CRT termi- nals; keyboards, display, and communication interface. An- other application could be in a process controller to interface sensors, relays, and motor controls. The limitation of the ap- plication area for such a circuit is solely that of the designers imagination.

The I/O structure shown interfaces to the 8080 CPU using the bus architecture developed previously in this chap- ter. Either Isolated or Memory Mapped techniques can be used, depending on the system I/O environment.

The 8251 provides a serial data communication inter- face so that the system can transm it and receive data over communication links such as telephone lines.

3-9

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Intel 8080 manual Addressing, Interface Example, Memr to

8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.