Intel 8080 manual RLrL- rL rL rL-rL- rLrL, Interrupt Sequences

INTERRUPT SEQUENCES

The 8080 has the built-in capacity to handle external interrupt requests. A peripheral device can initiate an inter- rupt simply by driving the processor's interrupt (INT) line high.

The interrupt (INT) input is asynchronous, and a request may therefore originate at any time during any instruction cycle. Internal logic re-clocks the external re- quest, so that a proper correspondence with the driving clock is established. As Figure 2-8 shows, an interrupt request (I NT) arriving during the time that the interrupt enable line (I NTE) is high, acts in coincidence with the ~2 clock to set the internal interrupt latch. This event takes place during the last state of the instruction cycle in wh ich the request occurs, thus ensuring that any instruction in progress is completed before the interrupt can be processed.

The INTERRUPT machine cycle which follows the

arrival of an enabled interrupt request resembles an ordinary FETCH machine cycle in most respects. The M1 status bit is transmitted as usual during the SYNC interval. It is accompanied, however, by an INTA status bit (DO) which acknowledges the external request. The contents of the program counter are latched onto the CPU's address lines during T 1, but the counter itself is not incremented during the INTERRUPT machine cycle, as it otherwise would be.

In this way, the pre-interrupt status of the program counter is preserved, so that data in the counter may be restored by the interrupted program after the interrupt request has been processed.

The interrupt cycle is otherwise indistinguishable from an ordinary FETCH machine cycle. The processor itself takes no further special action. It is the responsibility of the peripheral logic to see that an eight-bit interrupt instruction is "jammed" onto the processor's data bus during state T3. In a typical system, this means that the data-in bus from memory must be temporarily disconnected from the pro- cessor's main data bus, so that the interrupting device can command the main bus without interference.

The 8080's instruction set provides a special one-byte call which facilitates the processing of interrupts (the ordi- nary program Call takes three bytes). This is the RESTART instruction (RST). A variable three-bit field embedded in the eight-bit field of .the RST enables the interrupting device to direct a Call to one of eight fixed memory locations. The decimal addresses of these dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. Any of these addresses may be used to store the first instruction (s) of a routine designed to service the requirements of an interrupting device. Since the (RST) is a call, completion of the instruction also stores the old program counter contents on the STACK.

		M1	M2	M3
T3	T1	T2	T3 T4 Ts T1 T2 T3 T1	T2 T3
_n	n	r~	rLrL-rL"-rLrL-rL-rLrL

_---r~U~~Ur--LLJl.LIl.J\.J\U\Wl.Lr\.Jl..Jl.
A1S-0 pc·,	I pc	\	--- ~-I	sP·'		X SP·2
	Do \ ---RST--		~--1 --	X	PCH	X X	PCl
	(INTA)

SYNC

DBIN

I \ I r M

\

'---' L -

RETURN M1, - (INTERNAL) -~\

INTE

INTI

~

INT F/F (INTERNAL)

INHIBIT STORE OF PC+1 (INTERNAL)

STATUS INFORMATION

I\

I\

0---X\@A\@

NOTE: ® Refer to Status Word Chart on Page 2-6.

Figure 2-8. Interrupt Timing

2-11