Intel 8080 manual TYPICAL!J. Output Delay VS. ~ Capacitance

SILICON GATE MOS 8080A-1

A.C. CHARACTERISTICS (Continued)

TA =O°C to 70°C, Vo o =+12V ± 5%, Vee = +5V ± 5%, Vss = -5V ± 5%, Vss = OV, Unless Otherwise Noted

Symbol tOS2 tOH [1] tiE [2] tRS tHS tiS

tH tFO tAW [2] tOW[2] two [2] tWA [2]

Parameter

Data Setup Time to ¢2 During DBIN Data Hold Time From ¢2 During DBIN INTE Output Delay From ¢2 READY Setup Time During ¢2 HOLD Setup Time to ¢2

INT Setup Time During ¢2 (During <t>1 in Halt Mode) Hold Time From ¢2 (REAOY, INT, HOLD)

Delay to Float During Hold (Address and Oata Sus) Address Stable Prior to WR

Output Data Stable Prior to WR

Output Data Stable From WR

Address Stable From WR

Min.	Max. Unit	Test Condition
120	nsec

[1]nsec

200 nsec CL = 50pf

90nsec

120nsec

100nsec

0nsec

120 nsec

[5]	nsec	........,
[6]	nsec
[7]	nsec
[7]	nsec	~ CL = 50pf: Address, Data

CL=50pf: WR, HLDA, DBIN

tHF[2]

tWF[2] tAH [2]

H LDA to Float Delay	[8]	nsec
WR to Float Delay	[9]	nsec
Address Hold Time After DBIN During HLDA	-20	nsec	-

NOTES:

1.Data input should be enabled with OBIN status. No bus conflict can then occur and data hold time is assured. tOH :::: 50 ns or tOF, whichever is less.

2.Load Circuit.

+5V

9

2.1K

8080A

OUTPUT

A1S -AO ~

twA3. tCY:::: t03 + t nt>2 + t4>2 + tf4>2 + t02 + t r4>1 ;> 320ns.

	I- -		TYPICAL!:J. OUTPUT DELAY VS. ~ CAPACITANCE
0 7 -00				+20 r ------- . ----------- r ----		----- ,
	two		.5-
SYNC			>	+10
			~
			...J
			W
			0	0
oBIN			~
			::::>
			Q.
			~
			::::>	-10
			0
WR			-1
	toc			-50	o	+50	+100
READY					~ CAPACITANCE (pf)
					(CACTUAL - CSPEC )
WAIT		4. The following are relevant when interfacing the 8080A to devices having VIH :::: 3.3V:
			a) Maximum output rise time from .8V to 3.3V = 1OOns @ CL =SPEC.
HOLD	I -		b) Output delay when measured to 3.0V = SPEC +60ns @ CL = SPEC.
	---. t oc .--		c) If CL :f. SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL < CSPEC.
		5.	tAW:::: 2 tCY -t03 -tnt>2	-110nsec.
HLoA		6.	tOW:::: tCY -t03 -tr</>2 -150nsec.
		7. If not HLDA, tWO:::: tWA:::: t03 + t r<P2 +10ns. If HLOA, tWO:::: twA :::: tWF.
		8.	t HF :::: t03 + t r<P2 -50ns.
INT		9.	tWF = t03 + t r4>2 -10ns
		10. Data in must be stable for this period during DB IN ·T3. Both tOS1 and tOS2 must be satisfied.
		11. Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.)
		12. Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3, T4, TS
			and TWH when in hold mode. (External synchronization is not required.)
INTE		13.	Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be
			recognized on the following instruction. (External synchronization is not requiredJ
		14. This timing diagram shows timing relationships only; it does not represent any s~ific machine cycle.

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