Intel 8080 manual Fft~l, ~tOF.I, ~-t

SILICON GATE MOS 8080A-1

A.c. CHARACTERISTICS CA UTlON: When operating the 8080A·l at or near full speed, care must be taken to assure precise timing compatibility between 8080A·', 8224 and 8228.

TA =O°C to 70°C, Voo =+12V ± 5%, VCC = +5V ± 5%, VSS =-5V ± 5%, VSS = OV, Unless Otherwise Noted

Symbol	Parameter	Min.	Max.	Unit	Test Condition
tCy[3]	Clock Period	.32	2.0	J.1sec
t r , tf	Clock Rise and Fall Time	0	25	nsec
t4»1	¢1 Pulse Width	50		nsec
t4»2	~ Pulse Width	145		nsec
t01	Delay cfJ1 to cfJ2	0		nsec
t02	Delay ¢2 to cfJ1	60		nsec
t03	Delay ¢, to ¢2 Leading Edges	60		nsec	} Cl = 50pf
tOA [2]	Address Output Delay From ¢2		150	nsec
too [2]
	Data Output Delay From ¢2		180	nsec	}C =50pf
toc[2]	Signal Output Delay From ¢" or cfJ2 (SYNC, WR.WAIT, HLOA)	25	110	nsec
tOF [2]	DBIN Delay From ¢2		130	nsec	l
tOI[1]	Delay for Input Bus to Enter Input Mode		tOF	nsec
tOS1	Data Setup Time During cfJ1 and DBIN	10		nsec

TIMING WAVEFORMS [14]	(Note: Timing measurements are made at the following reference voltages: CLOCK 111" = 8.0V
	110" = 1.0V; INPUTS 111" = 3.3V, 1'0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = O.8V.)

. t CY

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DBIN

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HOLD

HLDA

INT

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