Intel 8080 manual BIT 256 x 4 Static Cmos RAM

intele Silicon Gate CMOS 5101, 5101-3, 5101L, 5101L·3

1024 BIT (256 x 4) STATIC CMOS RAM

*Ultra Low Standby Current: 15 nA/Bit for the 5101

•	Fast Access Time - 650 ns	•	Directly TTL Compatible - All
•	Single +5 V Power Supply		Inputs and Outputs
		•	Three-State Output
•	CE2 Controls Unconditional

Standby Mode

The Intel® 5101 and 5101-3 are ultra-low power 1024 bit (256 words x 4-bits) static RAMs fabricated with an advanced ion- implanted silicon gate CMOS technology. The devices have two chip enable inputs. When CE 2 is at a low level, the minimum standby current is drawn by these devices, regardless of any other input transitions on the addresses and other control inputs. Also, when CEl is at a high level and address and other control transitions are inhibited, the minimum standby current is drawn by these devices. When in standby the 5101 and 5101-3 draw from the single 5 volt supply only 15 microamps and 200 microamps, respectively. These devices are ideally suited for low power applications where battery operation or battery backup for non-volatility are required.

The 5101 and 5101-3 use fully DC stable (static) circuitry; it is not necessary to pulse chip select for each address transition. The data is read out non-destructively and has the same polarity as the input data. All inputs and outputs are directly TTL compatible. The 5101 and 5101-3 have separate data input and data output terminals. Art output disable function is provided so that the data inputs and outputs may be wire OR-ed for use in common data I/O systems.

The 5101 Land 5101 L-3 are identical to the 5101 and 5101-3, respectively, with the additional feature of guaranteed data retention at a power supply voltage as low as 2.0 volts.

A pin compatible N-channel static RAM, the Intel 2101, is also available for low cost applications where a 256 x 4 organi- zation is needed.

The Intel ion-implanted, silicon gate, complementary MOS (CMOS) allows the design and production of ultra-low power, high performance memories.

PIN CONFIGURATION	LOGIC SYMBOL	BLOCK DIAGRAM
5101	5101

A3		22	Vee					@ V
					Ao			~ec
A2	2	21	A4					~GNO
					A,		ROW	CELL ARRAY
			RIW		A2		DECODERS	32 ROWS
A,	3	20						32 COLUMNS
Ao	4	19	CE1		A3
					A4
As	5	18	00		As
~	6	17	CE2		~
					A7
A7	7	16	004
					01,	DO,		DO,
GNO	8	15	014
					01 2	002
01,	9	14	003		013	003
DO,	10	13	01 3		014	004
					00
01 2	11	12	002
					RIW CE2	CE1
		PIN NAMES					@
	011 -01 4	DATA INPUT		00	OUTPUT DISABLE
							00
	Ao-A.,	ADDRESS INPUTS		00,- 004 OATA OUTPUT
								o =PIN NUMBERS
	RIW	READIWRITE INPUT		Vee.	POWER (+5VI
	ffi,CE2	CHIP ENABLE

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