Intel 8080 manual Exchange stack top with Hand L, ~ Sp +, ~ data, Cycles States Flags None

XTHL	(Exchange stack top with Hand L)
(L)	~((SP))
(H)	~ ((SP) + 1)

The content of the L register is exchanged with the content of the memory location whose address is specified by the content of register SP. The content of the H register is exchanged with the content of the memory location whose address is one more than the content of register SP.

1 I I 0 o o

Cycles: 5

States: 18

Addressing: reg. indirect

Flags: none

SPHL (Move HL to SP)

(SP) ~ (H) (L)

The contents of registers Hand L (16 bits) are moved to register SP.

1 I 1 I o o

Cycles: 1

States: 5

Addressing: register

Flags: none

IN port	(I nput)
(A)	~ (data)

The data placed on the eight bit bi-directional data bus by the specified port is moved to register A.

1 I	I 0 I	I 1 I 0 I 1 I 1
	port
	Cycles:	3
	States:	10
	Addressing:	direct
	Flags:	none

OUT port (Output) (data) ~ (A)

The content of register A is placed on the eight bit bi-directional data bus for transmission to the spec- ified port.

o o

port

Cycles: 3

States: 10

Addressing: direct

Flags: none

EI		(Enable interrupts)
The interrupt system is enabled following the execu-
tion of the next instruction.					,
1	I	I	1			I	1	I	1
					0
		Cycles:		1
		States:		4
		Flags:		none

01(Disable interrupts)

The interrupt system is disabled immediately fol- lowing the execution of the 01 instruction.

	1	1	0 1	0	' 1	1 1
	Cycles:		1
	States:		4
	Flags:		none
HLT	(Halt)
The processor is stopped. The registers and flags are
unaffected.
0 I 1 I			0 I 1 I 1 I 0
	Cycles:		1
	States:		7
	Flags:		none
NOP	(No op)
No operation is performed. The registers and flags
are unaffected.
0 I	0 I 0	0	0	0	0	0
	Cycles:		1
	States:		4
	Flags:		none

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