Instruction SET | Intel 8080 guide

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INSTRUCTION SET

Summary of Processor Instructions

By Alphabetical Order

				Instrumon Cod.lll					Clock121
Mnemonic	Desaiptioll	07	06	0 5	04	03	02	01 DO	Cychs
ACI	Add immediate to A with
	tarry
AOC M	Add memory to A with tarry	1	0	0	0	1	1		7
ADCr	Add register to A with carry	1	0	0	D	1	S		4
ADD M	Add memory to A	1	0	0	0	0	1		7
AOOr	Add register to A	1	0	0	0	0	S		4
AOI	Add immediate to A	1	1	0	0	0	1		7
ANAM	And memory with A	1	0	1	0	0	1		7
ANAr	And register with A	1	0	1	0	0	S		4
ANI	And immediate with A	1	1	1	0	0	1		7
CALL	Call ullCondi1ional	1	1	0	0	1	1		17
CC	Call on carry	1	1	0	1	1	1		11/17
CM	Call on minus	1	1	1	1	1	I		11/17
Cl1A	Compliment A	0	0	1	0	1	1		4
CMC	Compliment carry	0	0	1	1	1	1		4
CMPM	Compare memory with A	1	0	1	1	I	1		7
CMPr	Compare register with A	1	0	1	1	1	S		4
CNC	Call on no carry	1	1	0	1	0	1		11/17
CNZ	Call on no lero	1	1	0	0	0	1		11/17
CP	Call on positive	1	1	1	1	0	1		11/17
CPE	Call on parity even	1	1	1	0	1	1		11/17
CPI	Compare immediate with A	1	1	1	1	1	1		7
CPO	Call on parity odd	1	1	1	0	0	1		11/17
CZ	Call OnltrO	1	1	0	0	1	1		11/17
DAA	Decimal adjust A	0	0	1	0	0	1		4
DAD a	Add a & Cto H & L	0	0	0	0	1	0		10
DAD 0	Add 0 & E to H & L	0	0	0	1	1	0		10
DAD H	Add H & Lto H & L	0	0	1	0	1	0		10
DAD SP	Add stack pointer to H & L	0	0	1	1	1	0		10
OCR M	Decrement memory	0	0	1	1	0	1		10
OCR r	Decrement register	0	0	0	D	0	1		5
DCX 8	Decrement B & C	0	0	0	0	1	0		5
DCX D	Decrement 0 & E	0	0	0	1	1	0		5
OCX H	Decrement H& L	0	0	1	0	1	0		5
OCXSP	Decrement stack po inter	0	0	1	1	1	0		5
01	Disable Interrupt	1	1	1	1	0	0		4
EI	Enable Interrupts	I	1	1	1	1	0		4
HLT	Halt	0	1	1	1	0	1	0	7
IN	Input	1	1	0	1	1	0	1	10
INR M	Increment memory	0	0	1	1	0	1	0	10
INR r	Increment register	0	0	0	0	D	1	0	5
INX8	Increment a & Cregisters	0	0	0	0	0	0	1	5
INX 0	Increment 0 & Eregisters	0	0	0	1	0	0	1	5
INX H	Increment H & Lregisters	0	0	1	0	0	0	1	5
INXSP	Increment stack pointer	0	0	1	1	0	0	1	5
JC	Jump on carry	1	1	0	1	1	0	0	10
JM	Jump on minus	1	I	1	1	1	0	0	10
JMP	Jump unconditional	1	1	0	0	0	0	1	10
JNC	Jump on no carry	1	1	0	1	0	0	0	10
JNZ	Jump on no lero	1	1	0	0	0	0	0	10
JP	Jump on positive	1	1	1	1	0	0	0	10
JPE	Jump on parity even	1	1	1	0	1	0	0	10
JPO	Jump on parity odd	1	1	1	0	0	0	0	10
JZ	Jump onlero	1	1	0	0	1	0	0	10
LOA	Load A direct	0	0	1	1	1	0	0	13
LOAXa	Load A indirect	0	0	0	0	1	0	0	7
LOAX 0	Load A indirect	0	0	0	1	1	0	0	7
LHLD	Load H & Ldinct	0	0	1	0	1	0	0	16
LXI8	Load immediate register	0	0	0	0	0	0	1	10
	Pair a & C
LXIO	Load immediate register								10
	Pair 0 & E
LXI H	Load immediate register								10
	Pair H & L
LXI SP	Load immed iate steck pointer								10

		Illstrudion Cod.(1)						C1cckl2J
Mn.mollie	Description	07 06 05 04 03			02	01	Do	Cychs
MVI M	Move immediate memory	1	1	0	1	1	0	10
MVlr	Move immediate register	D	D	0	1	1	0	7
MOVM.r	Move register to memory	1	1	0	S	S	S	7
MOVr,M	Move memory to register	0	D	0	1	1	0	7
MOV rt ,r2	Move register to register	0	D	0	S	S	S	5
NOP	No-operation	0	0	0	0	0	0	4
DRAM	Or memory with A	1	1	0	1	1	0	7
ORAr	Or register with A	1	1	0	S	S	S	4
ORI	Or immediate with A	1	1	0	1	1	0	7
OUT	Output	0	1	0	0	1	1	10
PCHL	H & L to program counter	1	0	1	0	0	1	5
POP 8	Pop regi$ter pair a & Coff	0	0	0	0	0	1	10
pop 0	stick
pop 0	Pop register pair 0 & E off							10
	stack
POP H	Pop register pair H & L off							10
	stack
POP PSW	Pop Aand Flags							10
	all stack
PUSH 8	Push register Pa ir 8 & Con							11
	stack
PUSH 0	Push register Pair 0 & Eon							11
	stack
PUSH H	Push register Pair H & L on							11
	stack
PUSH PSW	Push Aand Flags							11
	on stack
RAL	Rotlle A left through carry
RAR	Rolate A right through
	carry
RC	Return on carry	0	1	1		0		5'11
RET	Return	0	0	I		0		10
RLC	Rotate A left	0	0	0		1		4
RM	Return on minus	1	1	1		0		5'11
RNC	Return on no carry	0	1	0		0		5'11
RNZ	Return on no lero	0	0	0		0		5'11
RP	Relurn on positive	1	1	0		0		5111
RPE	Return on parity even	1	0	1		0		5'11
RPO	Return on parity odd	1	0	0		0		5'11
RRC	Rotate A right	0	0	1		1		4
RST	Restart	A	A	A		1		11
RZ	Return on lero	0	0	1		0		5'11
SaB M	Subtract memory Irom A	0	1	1		1		7
	with borrow
SBa r	Subtract register from A
	with borrow
S81	Subtract immediate from A
	with borrow
SHLO	Slore H & Ldirect				0		0	16
SPHL	H& Lto stack pointer				0		1	5
STA	Store A direct				0		0	13
STAX 8	Slore A indirect				0		0	7
STAX 0	Store A indirect				0		0	7
STC	Sel ClIrry				1		1	4
SUB M	Subtract memory from A				1		0	7
SU8 r	Subtract register Ira m A				S		S	4
SUI	Subtrlct immediate from A				1		0	7
XCHG	Exchange 0 & E. H & L				0		1	4
	Registers
XRAM	Exclusive Or memory with A
XRA r	Exclusive Or register with A
XRI	Exclusive Or immediate with
	A
XTHL	Exchange to p 01 stack, H & L							18

NOT ES: 1. 0 DO or SSS - 000 B - 001 C - 010 0 - 011 E - 1OOH - 101 L - 110 Memory - 111 A. 2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags.

Image 259

Intel 8080 manual Instruction SET, Summary of Processor Instructions By Alphabetical Order

8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.

Contents

Page Programmable Peripheral Interface Clock Generator for 8080ASystem Controller for 8080A Programmable Communication Interface Contents Peri pherals 127Chapter Packaging Information Page Microcomputer Design Aids Advantages of Designing With MicrocomputersConventional System Programmed Logic Iii Applications Example1IIII~Iff1 Peripheral Devices Encountered Application Architecture of a CPU Typical Computer SystemAccumulator Instruction Register and Decoder Program Counter Jumps, Subroutines and the Stack Computer Operations Control CircuitryAddress Registers Arithmetic/Logic Unit ALU Wait memory synchronization Instruction FetchMemory Read Memory WritePage Page 8080 Photomicrograph With Pin Designations INTE~ Registers Architecture of the 8080 CPU Processor Cycle Arithmetic and Logic Unit ALUInstruction Register and Control Data Bus Buffer Machine Cycle Identification Halt State Transition Sequence Status Bit Definitions Status Word ChartStatus Information Definition ?~~ CPU State Transition Diagram Rr\ ONE ,----- ~ ~2. State Definitions State Associated Activities Interrupt Sequences RLrL- rL rL rL-rL- rLrL ¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL Halt Sequences Hold SequencesSTART-UP of the 8080 CPU 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~iA~~~11 ~iA~~~11~iA~~ll,12 ~A~~~ll 111 000 001 010 011 100 101 Value Basic System Operation Typical Computer System Block Diagram Clock Generator Design CPU Module Design8080 CPU Clock Generator and High Level Driver ~50ns ClK 0.......-..-.-----.. tf1A TTLHigh Level Driver Design Ststb !1 Page ROM Interface Interfacing the 8080 CPU to Memory and I/O DevicesRAM Interface Ill Memory Mapped I/O InterfaceGeneral Theory Isolated I/O Interface Example AddressingMemr to 15 Format 13 Format 8080 Instruction SET Instruction and Data Formats Addressing Modes Byte OneByte Two Byte Three I D7 All Symbols and AbbreviationsSymbols Meaning Description Format Reg. indirect Content of register r2 is moved to register r1Data Transfer Group MOV r1, r2 Move Register 0 I R 0 I R p 0 I 0 o 0 IArithmetic Group 1 I 0 I D I D R 0 I Cycles States Addressing reg. indirect Flags Z,S,P ,CY,AC I ILogical Group OCR M Decrement memory 1 1 1 I 0 I 1 I 1 II 1 I 1 o I 1 I 1 I ~11~ Cycles States Flags none 0 I 1 I0 I 0 1 I 0 I 0 I 000 Branch Group Ccondition addr I c c I c I 0 I 0 ISP ~ SP + 1 I R Stack, I/O, and Machine Control GroupI 1 o Push rp Cycles States Flags None Exchange stack top with Hand L~ SP + ~ data Instruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page PIN Names Schottky Bipolar Clock Generator Functional DescriptionGeneral Oscillator Ststb Status Strobe Power-On Reset and Ready Flip-Flops Crystal Requirements Characteristics 8pF Input TORS tORH tOR FMAX Characteristics For tCY = 488.28 nsExample T42 T01 T02 T03 Toss Dbin PIN Configuration Block Diagram Block General Inta None Control Signals Hlda to Read Status Outputs Characteristics TA = Oc to 70C Vee = 5V ±5%TE~r Waveforms VCC=5V GoUTStstb VTH GND ---. r ·-c ?oo .H Intel Silicon Gate MOS 8080 a Vss Vee8080A Functional PIN Definition IOl = 1.9mA on all outputs CharacteristicsAbsolute Maximum RATINGS· Capacitance ~~1 t CY =..... -r-DATAIN~I~~~ Timing Waveforms Typical ~ Output Delay VS. a Capacitance Characteristics Typical Instructions Instruction SET Summary of Processor Instructions Silicon Gate MOS 8080.A Infel Silicon Gate MOS 8080A-1 Max Symbol Parameter TypUnit ~tOF.I Fft~l~-t TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 VAOOR/OATA = VSS + O.45V +10Cout J1A Unit Test Condition Symbol Parameter Min Min. Max. Unit Test Condition Typical ~ Output Delay VS. ~ CapacitancePage Intel . Silicon Gate MOS M8080A Interrupt instructions Immediate mode or I/O instructionsRegister to regist~r, memory refer Ence, arithmetic or logical, rotate Llf17 Summary of Processor Instructions M8080A Functional PIN Definition Silicon Gate MOS M8080A IOL = 1.9mA on all outputs Absolute Maximum RatingsOperation Symbol Parameter Min. Max Unit Test Condition ~I~ Silicon Gate MOS M8080APage ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A PIN Connections Operating CharacteristicsVoo = V ce Switching Characteristics1N= Vee ~10% Cs=o.~ \ \ SYMBOLTESTMIN. TYP. MAX. Unit Conditions Operating Characteristics for Programming OperationSymbol Test Characteristics for Programming Operation Program Operation Switching Characteristics for Programming OperationCS = OV Programming Operation of the 8702A Programming Instructions for the 8702A Operation of the 8702A in Program ModeII. Programming of the 8702A Using Intel Microcomputers III a Erasing ProcedurePage PIN Names PIN Configurations Block Diagram VOH1 CommentIII IBB Max Unit Symbol Parameter Typ. Max. Unit ConditionsTest Conditions Waveforms TpF Program Pulse Fall Time Parameter MinProgramming Current RnA Program Pulse Amplitude CS/WE = +12V Read/Program/Read Transitions+-------1 PEEEf!1EJEZPlEzz$m=2!·m·· Icc 150 r Silicon Gate MOS Outa CommentMAX Unit CS=O.O 100 ns 7001 JJ.s ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\200ns 500ns 300 ns Cs .. o.~ ~r Typical Characteristics Silicon Gate MOS ILO IlclIlpc Ilkc CoUT Conditions of Test for CharacteristicsCIN ~ ~ ~ Customer Number Oate Mask Option SpecificationsMarking Pppp 79-80 ~ r ------ + -- t --- . L . ------ rJTitle Card Blank Intel Silicon Gate MOS ROM 8316A PIN Configuration Block Diagram Conditions of Test for 400CAPACITANCE2 TA = 25C, f = 1 MHz Waveforms OU~TVALID ILICO.N Gate MOS ROM 8316A Typical D.C. Characteristics Mask Option Speci Fications CustomerNumber Oate STO COM~ANY Name Title Card RAMs Page Silicon Gate MOS PIN Configuration Logic Symbol Block Diagram +----+ ~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~== OC 10H = -150 p.A 00 ~ Conditions of TestPage Silicon Gate MOS PIN Configuration Logic Symbol Block Diagram ICC2 Symbol Parameter Min. Typ.rIII ICC1 Timing Measurement Reference Level Volt Write 1~-tAW--.I-----I550 200 Input Pulse Rise and Fall Times 20nsecPage Silicon Gate MOS TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified Power Dissipation Watt5V to +7V Comment Conditions of Test 85o-·-···T+--~~~TL~~~EEt~~~P-.± Capacitance T a = 25C, f = 1MHz ~~~b~.J Typical A.C. Characteristics Silicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 230 450300 Output Source Current VS VIN Limits VS. TemperatureAccess Time VS Ambient Temperature Access Time VS LOAD·CAPACITANCE PIN Configuration Logic Symbol Block Diagram Fully Decoded Random Access BIT Dynamic Memory IOOAV2 Silicon Gate MOS 81078·4 IMP~ri~~CE II.~ Write Cycle Read Cycle4000 Ref = Typical Characteristics RWc 590 CD Symbol Parameter Min MaxNumbers in parentheses are for minimum cycle timing in ns System Interfaces and Filtering Power DissipationStandby Power Refresh Typical System BIT 256 x 4 Static Cmos RAM Icccr ICC2VIH VOL VOH VOR Timing Measurement Reference Level Volt Input Pulse Rise and Fall Times 20nsec ~I----- t CW2 ------ . t Schottky Bipolar PIN Configuration Logic Symbol Voo- --- ---T Conditions of Test All driver outputs are in the state indicated Power Supply Current Drain and Power Dissipation Typical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page EIGHT-BIT INPUT/OUTPUT Port PIN Configuration Logic Diagram OS2 Functional Description Gated Buffer Basic Schematic SymbolsII. Gated Buffer 3·STATE Are 3-state BI-DIRECTIONAL BUS Driver III. Bi-Directional Bus DriverIV. Interrupting Input Port Interrupt Instruction Port OvJ \.. -4~ VI. Output Port With Hand-ShakingVII Status Latch 8080 4 System Viii SystemOUT Vee IX System 1G~D L-~ DalN-t?!NrJ Absolute Maximum Ratings· Characteristics 052 ~ Typical Characteristics Tpw OUT TA = OC to + 75C Vee = +5V ± 5% Switching Characteristics12 pF ~~~lEI~S 1-- +SV Programmable Peripheral Interface Basic Functional Description GeneralData Bus Buffer Read/Write and Control Logic Ports A, B, and C ResetPIN Configuration Group a and Group B Controls PA 7 ·pAo Mode SelectionSingle Bit Set/Reset Feature Detailed Operational Description Mode 0 Timing Operating Modes Mode 0 Basic Input/OutputInterrupt Control Functions Mode 0 Configurations Mode 0 Port Definition Chart 119 · / ,4 Operating Modes Mode 1 Strobed Input/Output Inte a Input Control Signal DefinitionIBF Input Buffer Full F/F Intr Interrupt Request Intea Output Control Signal Definition Output Operations Combinations of ModeBi-Directional Bus I/O Control Signal Definition Operating Modes Mode 2 Bi-directional Timing Mode 2 Control Word Mode 2 and Mode 0 Output Mode 2 Combinations Reading Port C Status Special Mode Combination ConsiderationsMode Definition Summary Table Source Current Capability on Port B and Port C Keyboard and Terminal Address Interface ApplicationsPrinter Interface Keyboard and Display Interface ~.LEFT/RIGHT PCO Silicon Gate MOS Time From STB = 0 To IBF Characteristics TA = oc to 70C Vee = +5V ±5% vss = OVVil Input Low Voltage Input High Voltage Val Output Low Voltage IOl = 1.6mA Mode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface ClK Clock Reset ResetGeneral ReadlWrite Control logic DTR Data Termin·al Ready Modem ControlDSR Data Set Ready TxE Transmitter Empty RxC Receiver Clock Receiver BufferReceiver Control RxRDY Receiver Ready Programming Mode InstructionCommand Instruction Detailed Operation Description Data C~~RACTER Mode Instruction DefinitionAsynchronous Mode Transmission Asynchronous Mode Receive Synchronous Mode, Transmission Format Synchronous Mode TransmissionSynchronous Mode Receive Mode Instruction Format, Synchronous Mode Status Read Format Command Instruction DefinitionCommand Instruction Format Status Read Definition Synchronous Interface to Telephone Lines Asynchronous Serial Interface to CRT Terminal, DC-9600 BaudAsynchronous Interface to Telephone Lines Synchronous Interface to Terminal or Peripheral Device Icc CapacitanceIOL Typ TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol Parameter RXD~ RxDSRX ~4IlI ~AST BIT ,----1 Peripherals Page High Speed 1 OUT of 8 Binary Decoder Decoder Enable GateSystem 24K Memory Interface Using a very similar circuit to the I/O port decoder, an arPort Decoder Chip Select Decoder Ill Logic Element Example\lJ JJ,.--+-I----.....1 8205 Characteristics TA = OOC to +75C, Vee = 5.0V ±5%Typical Characteristics Symbol VOL VOH Test Waveforms Switching Characteristics Conditions of Test Test LoadAddress or Enable to Output Delay VS. Load Capacitance Address or Enable to Output Delay VS. Ambient Temperature ~ R PIN Configuration~ ~ Polled Method Interrupts in Microcomputer SystemsInterrupt Method Current Status Register Priority Encoder AO, A1, A2 Control SignalsINTE, elK ElR, ETlG, ENGl Basic Operation Level Controller Level Controller I I Cascading Absolute Maximum Ratings Operating CharacteristicsSymbol Parameter Limits Unit Conditions Min Typ.£1 Los Characteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar 8216 8226 +-......---- n cs Control Gating OlEN, CS Bi-Directional Driver Memory and 1/0 Interface to a Bi-directional Bus Applications of 8216/8226Large microcomputer systems it is often necessary to pro Input Leakage Current OlEN, CS VR =5.25V IcC Power Supply Current 120Input Load Current OlEN, CS VF =0.45 Input Load Current All Other Inputs VF =0.45 OUT WaveformsPage 8253 8257 8259 Page It uses nMOS technology ~Jmodesof operation are Programmable Interval Timer System Interface Block DiagramPreliminary Functional Description System Interface Programmable DMA Controller Dack 2 System InterfaceSystem Application CS-------It LJJ Intel CPU GroupROMs RAMs Peripheral Coming Soon 735~ ~~~1It-j Lead CerDIP Dual IN-LINE Package D \.--.J.. ~~~l·34o~ Lead Plastic Dual IN-LINE Package P Sales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Summary of Processor Instructions By Alphabetical Order Instruction SET Microcomputer System Users Registration Card Microcomputer Systems Bowers Avenue Santa Clara, CA Intel Corporation Inter