Intel 8080 manual Port Decoder, Chip Select Decoder, 24K Memory Interface

SCHOTTKY BIPOLAR 8205

APPLICATIONS OF THE 8205

The 8205 can be used in a wide variety of applications in microcomputer systems. I/O ports can be decoded from the address bus, chip select signals can be generated to select memory devices and the type of machine state such as in 8008 systems can be derived from a simple decoding of the state lines (SO, S1, S2) of the 8008 CPU.

I/O Port Decoder

Shown in the figure below is a typical application of the 8205. Address input lines are decoded by a group of 8205s

(3). Each input has a binary weight. For example, AO is as- signed a value of 1 and is the LSB; A4 is assigned a value of 16 and is the MSB. By connecting them to the decoders as shown, an active low signal that is exclusive in nature and represents the value of the input address lines, is available at the outputs of the 8205s.

This circuit can be used to generate enable signals for I/O ports or any other decoder related application.

Note that no external gating is required to decode up to 24 exclusive devices and that a simple addition of an inverter or two will allow expansion to even larger decoder net- works.

Chip Select Decoder

Using a very similar circuit to the I/O port decoder, an ar-

Ao	Ao	°0
A,	A,	0,
A2	A2	°2
	8205	°3
		°4
A3	E;	Os
A4	E2
EN	E3
	Ao	°0
	A,	0,
	A2	°2	fo
		°3	fi
	8205		PORT
		°4	1"2 NUMBERS
	E;	°5	13
EN	~	°6	14
	E3		15
	Ao		i6
	A,	0,	17
	A2	°2	is
		°3	f9
	8205
			20
		°4
	~	°5	21
EN	E2	°6	22
	E3	°7	23

I/O Port Decoder

ray of 8205s can be used to create a simple interface to a 24K memory system.

The memory devices used can be either ROM or RAM and are 1K in storage capacity. 8308s and 8102s are the devices typically used for this application. This type of memory de- vice has ten (1 0) address inputs and an active "low" chip select (CS). The lower order address bits AO-A9 which come from the microprocessor are "bussed" to all memory ele- ments and the chip select to enable a specific device or group of devices comes from t~e array of 8205s. The output of the 8205 is active low so it is directly compatible with the memory components.

Basic operation is that the CPU issues an address to identify a specific memory location in which it wishes to "write" or "read" data. The most significant address bits A1O-A 14 are decoded by the array of 8205s and an exclusive, active low, chip select is generated that enables a specific memory de- vice. The least significant address bits AO-A9 identify a specific location within the selected device. Thus, all ad: dresses throughout the entire memory array are exclusive in nature and are non-redundant.

This technique can be expanded almost indefinitely to sup- port even larger systems with the addition of a few inverters and an extra decoder (8205).

Ao-Ag''-		_ :> ~~MORIES
A,O----~......-.-I Ao			~
All ---- . - .. - t -- I A,		0,	CS,
A'2 --- "" - '+ -- + --- 4A			CS	2
	2
		8205	CS3
			CS4
	~		CSs
	E;		CS6
	E3		CS;
	Ao		cs;
	A,		csg
	A2		CS,o
		8205	CSll		CHIP
					SELECTS
			CS'2
	~		CS t3
GND	e;		CS'4
	E3		~
	Ao		CS'6
	A,	~	CS17
	A2		CS'8
		8205	CS'9
			CS20
	e;
			CS2,
	e;		CS22
	E3		CS23

24K Memory Interface

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