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Intel 8080 manual ~~~H --4!~--~N-~-TA-AL-~-DU-T--~, 100 ns 7001 JJ.s, 200ns 500ns 300 ns

Models: 8080

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SILICON GATE MOS 8302

A.C. Characteristics

TA =(1J C to +70°C, Vee =+5V ±5%, V

= -9V ±5%, V = -9V ±5% unless otherwise noted

oo

GG

SYMBOL

Freq. tOH tACC

tovGG t cs

tco too t OHC

TEST

Repetition Rate

Previous read data val id

Address to output delay

Clocked VGG set up

Ch ip select delay

Output delay from CS

Output deselect

Data out hold in clocked VGG mode (Note 1)

MINIMUM TYPICAL MAXIMUM UNIT

1 MHz

100 ns

.7001 JJ.s

1

JJ.s

200ns

500ns

300 ns

5JJ.s

Note 1. The output will remain valid for tOHC as long as clocked VGG is at Vce. An address change may occur as soon as the output is sensed (clocked VGG may still be at Vee). Data becomes invalid for the old address when clocked VGG is returned to VGG.

Capacitance* TA = 25°C

SYMBOL

TEST

MINIMUM TYPICAL

C ,N

Input Capacitance

5

COUT

Output Capacitance

5

C VGG

VGG Capacitance

 

 

(Clocked VGGMode)

 

*This parameter is periodically sampled and is not 100% tested.

Switching Characteristics

Conditions of Test:

Input pulse. amplitudes: 0 to 4V; t R , t F ~ 50 ns Output load is 1 TTL gate; measurements made

at. output of TTL gate (tpD ::5 15 ns)

A) Constant VGG Operation

-- CYCLE TIME' I/FREO -

V

, ---------- _

IH

V 10%

 

 

V

ADDRESSfi 90%

 

 

A

cs

n'I I

I:t

V1L

1

 

 

I ~----

 

--I 'cs ~

 

I

_ V1H

 

 

 

-- t oH --l

V1L

:

 

 

:

 

I

 

 

I

g~~~H --4!~--~N-~-TA-AL-~-DU-T--~\

r;-

VOL

....1·----tAcc-----·~1

t---+--

 

DATA OUT

 

 

 

 

INVALID

 

DESELECTION OF DATA OUTPUT IN OR·TlE OPERATION

VIL'~

 

 

X"----

AD:~:Y::

 

 

 

V 1H

--- f

 

10%

 

 

 

 

 

CS

 

 

 

 

V1L

 

1

 

 

 

 

- too ~

 

"o~---f()

1

 

I

UI

 

 

 

 

DATA

 

I

 

OUT

 

I

 

VOL

 

I

 

 

 

---l t co .-

 

MAXIMUM

UNIT

CONDITIONS

10

pF

"1N= vee}

All

10

pF

CS = VCC

unused pins

30

pF

VOUT = VCC

are at A.C.

VGG = VCC

ground

 

 

B)Clocked VGG Operation

~CYCLE TIME ~ I FREO---....>ClADDRE~~H~::

V1L

I

 

I

 

I

 

I

VIH ,,:

 

I

I

I

CS

'\

~~ons---{

V1L

I

I

 

 

_I ~tDV

:.

 

Vee,; :GG

/: .. -------- .. \

CLOCKED

'\I

/ ;

~---

V VGG

I':

:(SEE NOTE 1)

GG

 

 

 

. - . - 'ACC ~ --I ~ t OHC

II

VOH-----~ I I

DATA

DATA OUT

I

I

DATA OUT

 

OUT

INVALID

 

 

INVALID

 

 

VOL ---------r--ISr----------

V,H

-v.DESELECTlDN OF DATA OUTPUT IN OR·TlE OPERATION

ADDRESS

.fi.

 

 

 

 

 

V1L

1-----------------

cs V

:

NOTE

2 . _

~

~ ~ Ons

~

,',r---~----l...·......i---

,H

 

 

 

 

 

 

'-"L

I

 

 

,I

I

 

~ " - to

 

 

too --,

I

~

 

GG

 

 

L: :

vcc,,: V

III

CLOCKED

I:

'I I

VGG

I

 

 

I

 

I

VGG

1-+1-----....",

 

 

I

I

 

I

 

...--~50ns---1 I

DATA O~HT

I

 

I

 

I

I

i-'ACC ~

 

 

 

.

V

 

 

 

 

 

{I:

VOL

 

......----------1

NOTE 1: The output will remain valid for tOHe as long as clocked VGG is at Vee. An address change may occur as soon as the output is sensed (clocked VGG may still be at Vee). Data becomes invalid for the old address when clocked VGG is returned to VGG'

NOTE 2: If CS makes a transition from VI L to VIH while clocked VGG is at VGG, then deselection of output occurs at too as shown in static operation with constant VGG'

5-53

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Page 117
Image 117
Intel 8080 manual ~~~H --4!~--~N-~-TA-AL-~-DU-T--~, 100 ns 7001 JJ.s, 200ns 500ns 300 ns
Page 116 Page 118