Intel 8080 manual Instruction SET

INSTRUCTION SET

Summary of Processor Instructions

Mnemonic	Description			Instruction Code 11 J						Clock(2)
		07	06	Os	04	03	02	0,	Do	Cycles
MOV r1 •r2	Move register to register	0	1	0	0	0	S	S	S	5
MOVM.r	Move register to memory	0	1	1	1	0	S	S	S	7
MOVr.M	Move memory to register	0	1	0	0	0	1	1	0	7
HLT	Halt	0	1	1	1	0	1	1	0	7
MVI r	Move immediate register	0	0	0	0	0	1	1	0	7
MVIM	Move immediate memory	0	0	1	1	0	1	1	0	10
tNR r	Increment register	0	0	0	0	0	1	0	0	5
OCR r	Decrement register	0	0	0	0	0	1	0	1	5
INR M	Increment memory	0	0	1	1	0	1	0	0	10
OCR M	Decrement memory	0	0	1	1	0	1	0	1	10
AOOr	Add register to A	1	0	0	0	0	S	S	S	4
AOCr	Add register to A with carry	1	0	0	0	1	S	S	S	4
SUB r	Subtract register from A	1	0	0	1	0	S	S	S	4
SBB r	Subtract register from A	1	0	0	1	1	S	S	S	4
	with borrow
ANAr	And register with A		0				S		S
XRA r	Exclusive Or register with A		0				S		S
ORA r	Or register with A		0				S		S
CMPr	Compare register with A		0				S		S
ADO M	Add memory to A		0				1		0
AOC M	Add memory to A with carry		0				1		0
SUB M	Subtract memory from A		0				1		0
SBB M	Subtract memory from A		0				1		0
	with borrow
ANA M	And memory with A
XRA M	Exclusive Or memory with A
ORA M	Or memory with A
CMPM	Compare memory with A
AOI	Add immediate to A
ACI	Add immediate to A with
	carry
SUI	Subtract immediate from A
SBI	Subtract immediate from A
	with borrow
ANI	And immediate with A
XRI	Exclusive Or immediate with
	A
ORI	Or immediate with A	1	1	1		0				7
CPt	Compare immediate with A	1	1	1		1				7
RLC	Rotate A left	0	0	0		0				4
RRC	Rotate A right	0	0	0		1				4
RAL	Rotate A left through carry	0	0	0		0				4
RAR	Rotate A right through	0	0	0		1				4
	carry
JMP	Jump unconditional			0	0	0	0	1	1	10
JC	Jump on carry			0	1	1	0	1	0	10
JNC	Jump on no carry			0	1	0	0	1	0	10
JZ	Jump on zero			0	0	1	0	1	0	10
JNZ	Jump on no zero			0	0	0	0	1	0	10
JP	Jump on positive			1	1	0	0	1	0	10
JM	Jump on minus			1	1	1	0	1	0	10
JPE	Jump on parity even			1	0	1	0	1	0	10
JPO	Jump on parity odd			1	0	0	0	1	0	10
CALL	Call unconditional			0	0	1	1	0	1	17
CC	Call on carry			0	1	1	1	0	0	11/17
CNC	"Call on no carry			0	1	0	1	0	0	11/17
CZ	Call on zero			0	0	1	1	0	0	11/17
CNZ	Call on no zero			0	0	0	1	0	0	11/17
CP	Call on positive			1	1	0	1	0	0	11/17
CM	Call on minus			1	1	1	1	0	0	11/17
CPE	Call on parity even			1	0	1	1	0	0	11/17
CPO	Call on parity odd			1	0	0	1	0	0	11/17
RET	Return			0	0	1	0	0	1	10
RC	Return on carry			0	1	1	0	0	0	5/11
RNC	Return on no carry			0	1	0	0	0	0	5/11

Mnemonic	Description			Instruction Code 11 J						Clock (2)
		07	06	Os	04	03	02	0,	Do	Cycles
RZ	Return on zero			0	0	'1	0	0	0	5/11
RNZ	Return on no zero			0	0	0	0	C	0	5/11
RP	Return on positive			1	1	0	0	0	0	5/11
RM	Return on minus			1	1	1	0	0	0	5/11
RPE	Return on parity even			1	0	1	0	0	0	5/11
RPO	Return on parity odd			1 0 0 0 0 0						5/11
RST	Restart			A A A 1 1 1						11
IN	Input			0	1	1	0	1	1	10
OUT	Output			0	1	0	0	1	1	10
LXI B	Load Immediate register			0	0	0	0	0	1	10
	Pair B & C
LXIO	Load immediate register									10
	Pair 0 & E
LXI H	Load immediate register									10
	Pair H & L
LXI SP	Load immediate stack pointer									10
PUSH B	Push register Pair B & C on									11
	stack
PUSH 0	Push register Pair 0 & E on									11
	stack
PUSH H	Push register Pair H & L on									11
	stack
PUSH PSW	Push A and Flags									11
	on stack
POP B	Pop register pair B & C off									10
	stack
POP 0	Pop register pair 0 & E off									10
	stack
POP H	Pop register pair H & L off									10
	stack
POP PSW	Pop A and Flags									10
	off stack
STA	Store A direct						0			13
LOA	Load A direct						0			13
XCHG	Exchange 0 &E. H& L						0			4
	Registers
XTHL	Excnange top of stack, H& L	1	1	1	0	0	0	1	1	18
SPHL	H & L to stack pointer	1	1	1	1	1	0	0	1	5
PCHL	H & L to program counter	1	1	1	0	1	0	0	1	5
DAD B	Add B & C to H & L	0	0	0	0	1	0	0	1	10
DAD 0	Add D & E to H & L	(l	0	0	1	1	0	0	1	10
DAD H	Add H & L to H & L	0	0	1	0	1	0	0	1	10
DAD SP	Add stack pointer to H & L	0	0	1	1	1	0	0	1	10
STAX B	Store A indirect	0	0	0	0	0	0	1	0	7
STAX 0	Store A indirect	0	0	0	1	0	0	1	0	7
LOAX B	Load A indirect	0	0	0	0	1	0	1	0	7
LOAX 0	Load A indirect	0	0	0	1	1	0	1	0	7
INX B	Increment B& C registers	0	0	0	0	0	0	1	1	5
INX 0	Increment 0 & E registers	0	0	0	1	0	0	1	1	5
INX H	Increment H & L registers	0	0	1	0	0	0	1	1	5
INX SP	Increment stack pointer	0	0	1	1	0	0	1	1	5
OCX B	Decrement B & C	0	0	0	0	1	0	1	1	5
OCX 0	Decrement 0 & E	0	0	0	1	1	0	1	1	5
OCX H	Decrement H & L	0	0	1	0	1	0	1	1	5
OCX SP	Decrement stack pointer	0	0	1	1	1	. 0	1	1	5
CMA	Complement A	0	0	1	0	1	1	1	1	4
STC	Set carry	0	0	1	1	0	1	1	1	4
CMC	Complement carry	0	0	1	1	1	1	1	1	4
OAA	Decimal adjust A	0	0	1	0	0	1	1	1	4
SHLO	Store H & L direct	0	0	1	0	0	0	1	0	16
LHLO	Load H & L direct	0	0	1	0	1	0	1	0	16
EI	Enable Interrupts	1	1	1	1	1	0	1	1	4
01	Disable interrupt	1	1	1	1	0	0	1	1	4
NOP	No-operation	0	0	0	0	0	0	0	0	4

NOTES: 1. DOD or SSS - 000 B - 001 C - 2. Two possible cycle times, (5/11)

010 0 - 011 E - 100 H - 101 L - 110 Memory - 111 A. indicate instruction cycles dependent on condition flags.