Intel manual CPU Module Design, 8080 CPU, Clock Generator and High Level Driver

The following pages will cover the detailed design of the CPU Module with the 8080. The three Busses (Data, Address and Control) will be developed and the intercon- nection to Memory and I/O will be shown.

Design philosophies and system architectures pre- sented in this manual are consistent with product develop-

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ment programs underway at INTEL for the MCS-80. Thus, the designer who uses this manual as a guide for his total system engineering is assured that all new developments in components and software for MCS-80 from INTEL will be compatible with his design approach.

CPU Module Design

The CPU Module contains three major areas:

1.The 8080 Central Processing Unit

2.A Clock Generator and High Level Driver

3.A bi-directional Data Bus Driver and System Control Logic

The following will discuss the design of the three major areas contained in the CPU Module. This design is presented as an alternative to the Intel® 8224 Clock Gener- ator and Intel 8228 System Controller. By studying the alternative approach, the designer can more clearly see the considerations involved in the specification and engineering of the 8224 and 8228. Standard TTL components and Intel general purpose peripheral devices are used to implement

	GND	2		AO
		20
	+5V			Al
		11
	-5V			A2
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	+12V			A3
				A4
				AS
			8080	A6
			CPU	A7
		13		A8
	SYSTEM DMA REO.		HOLD	A9
				Al0
		14		All
	SYSTEM INT. REO.		tNT	A12
		16		A13
	INT. ENABLE		INTE	A14
				A15
	XTAL			WR
				DBIN
	0
				HLDA
		22	ct>1	DO
		15
			eJ>2	01
		24		02
	CLOCK		WAIT	03
		23
WAIT REO.	GENERATOR		READY	04
	DRIVER
				05
SYS. RESET		12	RESET
				06
		19
			SYNC	07

the design and to achieve operational characteristics that are as close as possible to those of the 8224 and 8228. Many auxiliary timing functions and features of the 8224 and 8228 are too complex to practically implement in standard components, so only the basic functions of the 8224 and 8228 are generated. Since significant benefits in system timing and component count reduction can be realized by using the 8224 and 8228, this is the preferred method of implementation.

1.8080 CPU

The operation of the 8080 CPU was covered in pre- vious chapters of this manual, so little reference will be made to it in the design of the Module.

2.Clock Generator and High Level Driver

The 8080 is a dynamic device, meaning that its inter- nal storage elements and logic circuitry require a timing reference (Clock), supplied by external cir- cuitry, to refresh and provide timing control signals.

The 8080 requires two (2) such Clocks. Their wave- forms must be non-overlapping, and comply with the timing and levels specified in the 8080 A.C. and D.C. Characteristics, page 5-15.

Clock Generator Design

The Clock Generator consists of a crystal controlled,

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AO

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Al

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A2

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A3

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A4

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AS

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A6

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A7

34ADDRESS BUS

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A9

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Al0

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All

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A12

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7	BI-DIREC-
		DATA BUS
3	TIONAL
4	BUS DRIVER
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6

1	STATUS STROBE	SYSTEM
		CONTROL

Figure 3-2. 8080 CPU Interface

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