SILICON GATE MOS 81078·4

Typical Current Transients Ys. Time

 

 

100

200

300

400

500

0

100

200

300

400

500

 

 

I

I

I

I

I

I

I

I

I

I

I

 

 

WRITE

\

 

 

J

READ

\

 

 

CE

 

~ CYCLE

 

 

CYCLE

 

 

 

30

A

 

 

 

 

J

 

 

 

 

 

 

20

 

 

 

 

 

 

 

 

 

Ice

10

 

 

 

 

 

 

V

 

 

(rnA)

0

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.0

 

 

 

 

 

 

 

 

 

 

 

 

1.5

 

 

 

 

 

 

 

 

 

 

 

NORMALIZED

1.0

 

 

 

 

 

-- f -....AP---....~~----IDo2 TYPICAL

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.5

 

 

 

 

 

 

 

 

 

 

 

a

20

Iss 10

(rnA)

0

-10

Applications

Refresh

The 81078-4 is refreshed by either a read cycle, write cycle, or read-modify write cycle. Only the selected row of niemory array is refreshed. The row address is selected by the input signals AO thru A5. Each individual row address must receive at least one refresh cycle within any two milliseconds time period.

If a read cycle is used for refreshing, then the chip select input, CS, can be a logic high or a logic low. If a write cycle or read-modify write cycle is used to refresh the device, then CS must be a logic high. This will prevent writing into the memory during refresh.

Power Dissipation

The operating power dissipation of a selected device is the sum of Voo x 100AV and Vss x Iss. For a cycle of 400ns and tCE of 230ns typical power dissipation is 456mW.

Standby Power

The 81078-4 is a dynamic RAM therefore when VCE = VILC very little power is dissipated. In a typical system most devices are in standby with VCE at VILC. During this time only leakage currents flow (Le., 1001, ICC1, Iss, 'LO', 'L 1). The power dissipated during this inactive period is typically 1.4mW. The typical power dissipa- tion required to perform refresh during standby is the refresh duty cycle, 1.3%, multiplied by the operating power dissipation, or 5.9mW. The total power dissipation during standby is then 7.3mW typical.

System Interfaces and Filtering

On the following page is an example of a 16K x 8 bit memory system. Device decoding is done with the CE in- put. All devices are unselected during refresh with CS. It is recommended that 1JJ.F high frequency, low induc- tance capacitors be used on double sided boards. VCC to VSS decoupling is required only on the devices located around the periphery of the array. For each 36 devices a 100JJ.F tantalum or equivalent capacitor should be placed from VOO to VSS close to the array.

5-89

Page 154 Page 156
Page 155
Image 155
Intel 8080 manual Refresh, Power Dissipation, Standby Power, System Interfaces and Filtering
Page 154 Page 156

8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.
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