SILICON GATE MOS M8080A

A.C. CHARACTERISTICS (Continued)

TA = -55°C to +125°C, VOO =+12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted.

Symbol

Parameter

Min. Max.

Unit

Test Condition

tOS2

Data Setup Time to ¢2 During DBIN

130

nsee

 

tOH [1]

Data Hold Time From ¢2 During DBIN

50

nsee

 

tiE (2)

INTE Output Delay From ¢2

200

nsee

CL = 50pf

tRS

READY Setup Time During ¢2

120

nsee

 

tHS

HOLD Setup Time to ¢2

140

nsee

 

tiS

INT Setup Time During ¢2 (During 4>1 in Halt Mode)

120

nsee

 

tH

Hold Time From ¢2 (READY, INT, HOLD)

0

nsee

 

tFD

Delay to Float During Hold (Address and Data Bus)

130

nsee

-

tAW [2]

Address Stable Prior to WR

[5]

nsee

tDW[2]

Output Data Stable Prior to WR

[6]

nsee

 

tWD[2]

Output Data Stable From WR

[7]

nsee

 

tWA [2]

Address Stable From WR

[7]

nsee

~ CL =50pf

tHF[2]

H LOA to Float Delay

[8]

nsee

 

tWF[2]

WR to Float Delay

[9]

nsee

 

tAH [2]

Address Hold Time After DBIN During HLDA

-20

nsee

-

 

 

 

 

NOTES:

1.Data input should be enabled with OBIN status. No bus conflict can then occur and data hold time is assured. tOH = 50 ns or tOF, whichever is less.

2.Load Circuit.

+5V

8080A OUTPUT

3. tey = t03 + t rq,2 + tq,2 + tfq,2 + tD2 + t rq,l ~ 480ns.

..........

~---.......-----..... ---

SYNC

DBIN

READY

WAIT

HOLD fa-

~ t oe ' -

HLDA

INT

INTE

TYPICAL ~ OUTPUT DELAY VS. ~ CAPACITANCE

+20 r-----~---~---_---_

oS

>

+10

 

 

 

 

«

 

 

 

 

 

..J

 

 

 

 

 

w

 

 

 

 

 

0

 

 

 

 

 

....

0

 

 

 

 

:::J

 

 

 

 

 

Q.

 

 

 

 

 

....

 

 

 

 

 

:::J

-10

 

 

 

 

0

 

 

 

 

 

 

 

 

 

-1

 

 

 

 

 

 

-20

-50

o

+50

+100

 

-100

~CAPAC IT ANCE (pf)

(CACTUAL - CSPEC )

4. The following are relevant when interfacing the M8080A to devices having VI H = 3.3V: a) Maximum output r'isetime from .8V to 3.3V = lOOns @ CL = SPEC.

b) Output delay when measured to 3.0V = SPEC +60n5 @ CL = SPEC.

d If CL * SPEC, add .6ns/pF if CL> CSPEC, subtract .3n5/pF (from modified delay) if CL < CSPEC.

5. tAW = 2 tey -t03 -t rct>2 -140nsec.

6. tow =tCY -t03 -trep2 -170nsec.

7. If not HLOA, two =tWA = t03 + t r¢2 +10ns. If HLOA, two = tWA = tWF· 8. t H F = t03 + t rq,2 -50ns.

9. tWF = tD3 + t r<t>2 -10ns

10. Data in must be stable for this period during DBIN ·T3. Both tOS1 and tOS2 must be satisfied.

11. Ready signal must be stable for this perio~ during T2 or TW. (Must be externally synchronized.)

12. Hold signal must be stable for this period during T 2 or TW when entering hold mode, and during T3, T 4, T 5 and TWH when in hold mode. (External synchronization is not required.~

13. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be recognized on the following instruction. (External synchronization is not required.)

14. This timing diagram shows timing relationships only; it does not represent any specific machine cycle.

5-34

Page 96
Image 96
Intel 8080 manual Characteristics, Symbol Parameter Min. Max Unit Test Condition

8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.