Intel 8080 85o-·-···T, +--~~~TL~~~EEt~~~P-.±, Capacitance T a = 25C, f = 1MHz, Conditions of Test

SILICON GATE MOS 8102-2

A.C. CHARACTERISTICS TA =ooe to 70oe, Vee =5V ±5% unless otherwise specified

--·---

LIMITS

SYMBOL

PARAMETER

r----

mT----

UNIT

READ CYCLE

_.~~_~..._...

l}YP._

...

..L _~?<~. _._

85o-·-···T

-._-"--r .-_._.- --"---'-

--tR-e------r-R--EA~D-C-Y--C-L-E--·-------_ ..---------

ns

~~~~~~~---

~--------

~-_ .._-----

~--~--

-_._ ~._------

~ ---

--~

-----~_. -_.-

-.---~-.- -----

-_.--.--.~-------.-----.--. ...

- - _..---- ---1------- ----t···--- _._.-

t A

ACCESS TIME

I

500

i

850

ns

teo

CHIP ENABLE TO OUTPUT TIME

.

:

I

500

ns

~ ------

_ ---

---+

.._--l-.

~ ---

t OH1

PREVIOUS READ DATA VALID WITH RESPECT

50

I

os

TO ADDRESS

:

---------- 4 ---------

------ ·l - _.-_..-- .. ---- ---~----.

PREVIOUS READ DATA VALID WITH RESPECT

a

I

1

ns

TO CHIP ENABLE

i

_____:"__

-- J -

_

WRITE CYCLE

--~-C----

~W-R-I-T-E-C-Y-C-L-E----------------

T--8-~-r--~-~-

!

M

------ . ---- + ---- . ----- ...--.-.-----

.... -- . -------------------..

--

. __ ....

__ 1_ --

-

+ .

-..-.-t-------

tAW

ADDRESS TO WRITE SETUP TIME

I

200'

:

!

ns

. ----- ------ +i..--.----+-.-.-----.--..---~---.-----~---

~_tw_p

+_ -R-IT-E-P-U-L-S- -W-IDTH

I~~

L_.

.+- ...-n_--li---ns_-

tWR

WRITE RECOVERY TIME

--t

50:

!

I

ns

-----------

1t-------------------------

+------

~~:-------

..~

i

::_:

-+--~_:_~_:_:_~_T_L~_~~EEt~~~P-.±--

=~=~L~==--

+---

~-:-

t cw

CHIP ENABLE TO WRITE SETUP TIME

I

750!

;

ns

(1)Typical values are for T A=250 C and nominal supply voltage.

			CAPACITANCE TA = 25°C, f = 1MHz
					._------_._-----	LIMITS (pF)
A. C. CONDITIONS OF TEST			SYMBOL		TEST
						TYP.	MAX.
Input Pulse Levels:	+0.65 Volt to 2.2 Volt				---------_.- - _.--.._---- --
Input Pulse Rise and Fall Times:		20nsec	CIN		INPUT CAPACITANCE	3	5
					(ALL INPUT PINS) ViN :: OV
Timing Measurement Reference Level:		1.5 Volt	COUT
Output Load:	1 TTL Gate and CL	= 100 pF			OUTPUT CAPACITANCE	7	10
					VOUT = OV
WAVEFORMS
READ CYCLE			WRITE CYCLE
t4-------tRC-----~				t4-------twc---------I~
ADDRESS
	teo
CHIP			CHIP		..-----tew~----~I
ENABLE			ENABLE
~----tA-----""					~~----twP------...I
DATA			READ/
OUT
			WRITE
					~----tow----~~
			DATA	DATA CAN	DATA STABLE
			IN	CHANGE

5-77