Intel 8080 manual 1N= Vee, ~10%, = V ce, Switching Characteristics, Vcc\~

SILICON GATE MOS 8702A

A.C. CHARACTERISTICS

TA =00 C to +70°C, V =+5V ±5%, V = -9V ±5%, V =-9V ±5% unless otherwise noted

ccooGG

SYMBOL

Freq. tOH tAcc

tovGG t es

teo too tOHC

TEST

Repetition Rate

Previous read data val id

Address to output delay

Clocked VGG set up [2]

Chip select delay

Output delay from CS

Output deselect

Data out hold in clocked VGG mode (Note 1)

MINIMUM TYPICAL MAXIMUM UNIT

1 MHz

100 ns

1.3p.s

1.0JlS

400 ns

900 ns

400 ns

5JlS

Note 1. The output will remain valid for tOHe as long as clocked VGG is at Vee. An address change may occur as soon as the output is sensed (clocked VGG may still be at Vee). Data becomes invalid for the old address when clocked VGG is returned to VGG.

2. For this option please specify 8702AL

CAPACITANCE*

SYMBOL	TEST	MINIMUM TYPICAL	MAXIMUM	UNIT		CONDITIONS
C1N	Input Capacitance	8	15	pF	'1N= Vee }		All
COUT	Output Capacitance	10	15	pF	CS = Vce		unused pins
CVGG	VGG Capacitance		30	pF	VOUT	= Vee	are at A.C.
					VGG	= Vce	ground
	(Clocked VGG Mode)

~This parameter is periodically sampled and is not 100% tested.

B) Clocked VGG Operation

SWITCHING CHARACTERISTICS

Conditions of Test:

Input pulse amplitudes: 0 to 4V; t R ' t F ::; 50 ns .

Output load is 1 TTL gate; measurements made at output of TTL gate (tpD ~ 15 ns)

A) Constant VGG Operation

ADDRESS I			--XI
			CYCLE TIME	I/F REO
V	I
	){~10%
1H
V1l	I.....------------J, .......----
	~ 90%
_ V1H	ill			t--toH--1
	----I t cs	~		I
cs	I I			':
V1l	:			I
				I
				I
VOH 7-				I
DATA	l			,

OUT

V1H	--- f		10%
cs
V1l		I
VOH ---fe'		I	- too -
		I	V
DATA		I
OUT		I
VOL		I
		- l	teo f -

ADDRESS		~	CYCLE: TIME - 1 FREO			xlI
		' -				~
	VIHXI,0"lo
	V I------------..J
		. 90%				• •
	1L						I~---
		I					1
	VIH	\11		1
'				I---~Ons_____':
Cs	V1L	\1--------11----------
				I
GG		-II.- t	DV	:
		"I	GG	/:
	Vcc\~ :			J		\--
CLOCKED		I:		: (SEE NOTE 11
V	Vee;
		r---- tACC ----i		-I ~. 'OHC
			I	I
DATA			I	I
			I	I
OUT
	V	v:DESELECTIDN OF DATA OUTPUT IN DR·TlE OPERATION
	,H	.A
ADDRESS
CS	V1L	1-----------------
	V	'\	,,,r---;;......---7
		I			I
		I	NOTE 2		- ,		~~Ons
	,H
	V1L	I					I
		~~t
					tOD~
			GG
VGG		I					L·'·';
			DV
	VCC,\':
CLOCKED		::		/			I I
	VGG	I "tl ------ JI					I
		I		~50ns	-	---:
		I
DATA ~~~:			\				{'
		: . - tACC --- \•					..J
	VOl~

NOTE 1: The output will remain valid tor tOHe as long as clocked VGG is at Vee. An address change may occur as soon as the output is sensed (clocked VGG may still be at Vee!. Data becomes invalid for the old address when clocked VGG is returned to VGG'

~OTE 2: It CS makes a transition from VI L to VIH while clocked VGG IS at VGG. then deselection of output occurs at too as shown in static operation with constant VGG.

5-39