Functional Description, OS2 | Intel 8080 manual

SCHOTTKY BIPOLAR 8212

Functional Description

Data Latch

The 8 flip-flops that make up the data latch are of a "0" type design. The output (Q) of the flip-flop will follow th~ data input (0) while the clock input (C) is high. Latching will occur when the clock (C) returns low.

The data latch is cleared by an asynchronous reset input (CLR). (Note: Clock (C) Overides Reset (CLR).)

Output Buffer

The outputs of the data latch (Q) are connected to 3-state, non-inverting output buffers. These buffers have a common control line (EN); this control line either enables the buffer to transmit the data from the outputs of the data latch (Q) or disables the buffer; forcing the output into a high impedance state. (3 -state)

This high-impedance state allows the designer to connect the 8212 directly onto the microprocessor bi-directional data bus.

Control Logic

The 8212 has control inputs 051, 052, MO and STB. These inputs are used to control device selec- tion, data latching, output buffer state and service request flip-flop.

DS1, DS2 (Device Select)

These 2 inputs are used for device selection. When OS1 is low and OS2 is high (OS1 • OS2) the device is selected. In the selected state the output buffer is enabled and the service request flip-flop (SR) is asynchronously set.

MD (Mode)

This input is used to control the state of the output buffer and to determine the source of the clock input

When MO is high (output mode) the output buffers are enabled and the source of clock (C) to the data latch is from the device selection logic (051 • OS2). When MD is low (input mode) the output buffer state is det~rmined by the device selection logic (OS1 • OS2) and the source of clock (C) to the data latch is the.STB (Strobe) input.

STB (Strobe)

This input is used as the clock (C) to the data latch for the input mode MO = 0) and to synchronously reset the service request flip-flop (SR).

Note that the SR flip-flop is negative edge triggered.

Service Request Flip-Flop

The (SR) flip-flop is used to generate and control interrupts in microcomputer systems. It is asyn- chronously set by the CLR input (active low). When the (SR) flip-flop is.set it is in the non-interrupting state.

The output of the (SR) flip-flop (Q) is connected to an inverting input of a "NOR" gate. The other input to the "NOR" gate is non-inverting and is connected to the device selection logic (081 • 082). The output of the "NOR" gate (INT) is active low (interrupting state) for connection to active low input priority generating circuits.

SERVICE REQUEST FF

DEVICE SELECTION

[I> -~

OS1

[g> OS2

~ MO ---- to4'__~

[jj>STB --............

OUTPUT

BUFFER

DATA LATCH

[[>012 -------- + -.....

ff§> D IS -------..............

~01 7 -------+-1-1

~D18-------~.....

IE> CLR ----- 001 ~~_.......--'

(ACTIVE LOW)

STB	MD (DS,-DS2)		DATA OUT EaUALS	CLR	(OS1-0S2)	STB	-SR	tNT
~ 0	0	0	3-STATE	0	0	0	,	,
,	0	0	3=STAte------	0	,	0	,	0
0	,	0	DATA LATCH	,	1	' -	0	0
,	,	0	DATA LATCH	,		' -
0	0	,	DATA LATCH	,	1	0	1	0
~0	-0,-1 ---	,	DATA IN	,	0	0	1	,
~0	-0,-1 ---	,	DATA IN	1	,	~I	,	0
,	,	,	DATA IN		-INTERNAL SR FLIP-FLOP

C'i:R - RESETS DATA LATCH

SETS SR FLlP·FLOP

(NO EFFECT ON OUTPUT BUFFER)

5-102

8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.

Intel 8080 manual Functional Description, OS2

Models: 8080