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Intel 8080 manual Mode 2 Combinations, Mode 2 and Mode 0 Output

Models: 8080

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SILICON GATE MOS 8255

MODE 2 AND MODE 0 (INPUT)

	PC3	INTRA
	PA7 -PAO
	~	OBFA
CONTROL WORD	PC6 .	ACKA
0 7 0 6 05 04 03 O2 0,	DO
	PC4	STBA
PC2.()	PC5	IBFA
1 = INPUT
O=OUTPUT		3
		3
	PC2.()	I/O

P~-PBO

MODE 2 AND MODE 1 (OUTPUT)

PC3

A. ~

PA77PAo ( 8

PC7

CONTROLWOR°PC6

2 0, DO

	0
	PC4
	PCs
			t-...
	PB7 -PBO	8	)
			)
	PC2
RO	PC,		ACK B

WRPCO

Mode 2 Combinations

MODE 2 AND MODE 0 (OUTPUT)

	PC3	INTRA
	PA7-PAo
	P~	OBFA
CONTROL WORD	PC6 .	ACKA
0 7 0 6 0 5 0 4 0 3 O2 0, DO	PC4 .
	PC4 .	STBA
PC2.()	PC5	IBFA
1 = INPUT	PC2.() .
0= OUTPUT		3
		3
		I I " I/O
RO
	PB7 -PBO	8
WR

MODE 2 AND MODE 1 (INPUT)

PC3

A -".

PA7 -PAo ~ 8

'f y

PC7

CONTROLWOR°PC6

2 0, DO

PC4

PCs

PB7 -PBOKA 8 I

PC2 .....,

RO.- PC,

PCO

5-125

Page 193

Image 193

Intel 8080 manual Mode 2 Combinations, Mode 2 and Mode 0 Output

Contents

Page System Controller for 8080A Clock Generator for 8080AProgrammable Communication Interface Programmable Peripheral InterfaceContents Peri pherals 127Chapter Packaging Information Page Microcomputer Design Aids Advantages of Designing With MicrocomputersConventional System Programmed Logic Iii Applications Example1IIII~Iff1 Peripheral Devices Encountered ApplicationArchitecture of a CPU Typical Computer SystemAccumulator Instruction Register and Decoder Program Counter Jumps, Subroutines and the StackAddress Registers Control CircuitryArithmetic/Logic Unit ALU Computer OperationsMemory Read Instruction FetchMemory Write Wait memory synchronizationPage Page 8080 Photomicrograph With Pin Designations INTE~Registers Architecture of the 8080 CPUInstruction Register and Control Arithmetic and Logic Unit ALUData Bus Buffer Processor CycleMachine Cycle Identification Halt State Transition SequenceStatus Bit Definitions Status Word ChartStatus Information Definition ?~~ CPU State Transition DiagramRr\ ONE ,----- ~ ~2. State Definitions State Associated ActivitiesInterrupt Sequences RLrL- rL rL rL-rL- rLrL¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL Halt Sequences Hold SequencesSTART-UP of the 8080 CPU 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~iA~~ll,12 ~iA~~~11~A~~~ll ~iA~~~11111 000 001 010 011 100 101 ValueBasic System Operation Typical Computer System Block Diagram8080 CPU CPU Module DesignClock Generator and High Level Driver Clock Generator Design~50ns ClK 0.......-..-.-----.. tf1A TTLHigh Level Driver Design Ststb !1 Page ROM Interface Interfacing the 8080 CPU to Memory and I/O DevicesRAM Interface Ill General Theory InterfaceIsolated I/O Memory Mapped I/OInterface Example AddressingMemr to 15 Format 13 Format8080 Instruction SET Instruction and Data FormatsByte Two Byte OneByte Three I D7 Addressing ModesSymbols Meaning Symbols and AbbreviationsDescription Format AllData Transfer Group Content of register r2 is moved to register r1MOV r1, r2 Move Register Reg. indirect0 I R 0 I R pArithmetic Group 0 I1 I 0 I 0 o0 I D I D R 0 ILogical Group I IOCR M Decrement memory Cycles States Addressing reg. indirect Flags Z,S,P ,CY,ACI 1 I 1 o I 1 I 1 I I 0 I 1 I 1 I~11~ 1 1 10 I 0 1 I 0 I 1 I0 I 0 I Cycles States Flags none000 Branch GroupCcondition addr I c c I c I 0 I 0 ISP ~ SP + I 1 o Stack, I/O, and Machine Control GroupPush rp 1 I R~ SP + Exchange stack top with Hand L~ data Cycles States Flags NoneInstruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page PIN Names Schottky BipolarGeneral Functional DescriptionOscillator Clock GeneratorStstb Status Strobe Power-On Reset and Ready Flip-FlopsCrystal Requirements Characteristics8pF InputExample Characteristics For tCY = 488.28 nsT42 T01 T02 T03 Toss TORS tORH tOR FMAXDbin PIN Configuration Block DiagramBlock GeneralInta None Control SignalsTE~r Characteristics TA = Oc to 70C Vee = 5V ±5%Waveforms Hlda to Read Status OutputsStstb GoUTVTH VCC=5VGND ---. r ·-c?oo .H Intel Silicon Gate MOS 8080 aVss Vee8080A Functional PIN Definition Absolute Maximum RATINGS· CharacteristicsCapacitance IOl = 1.9mA on all outputs~I~~~ =..... -r-DATAINTiming Waveforms ~~1 t CYTypical ~ Output Delay VS. a Capacitance CharacteristicsTypical Instructions Instruction SETSummary of Processor Instructions Silicon Gate MOS 8080.AInfel Silicon Gate MOS 8080A-1 Max Symbol Parameter TypUnit ~tOF.I Fft~l~-t TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 Cout +10J1A VAOOR/OATA = VSS + O.45VUnit Test Condition Symbol Parameter MinMin. Max. Unit Test Condition Typical ~ Output Delay VS. ~ CapacitancePage Intel . Silicon Gate MOS M8080A Register to regist~r, memory refer Immediate mode or I/O instructionsEnce, arithmetic or logical, rotate Interrupt instructionsLlf17 Summary of Processor InstructionsM8080A Functional PIN Definition Silicon Gate MOS M8080AIOL = 1.9mA on all outputs Absolute Maximum RatingsOperation Symbol Parameter Min. Max Unit Test Condition ~I~ Silicon Gate MOS M8080APage ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A PIN Connections Operating CharacteristicsVoo 1N= Vee Switching Characteristics~10% = V ceCs=o.~ \ \Symbol Test Operating Characteristics for Programming OperationCharacteristics for Programming Operation SYMBOLTESTMIN. TYP. MAX. Unit ConditionsCS = OV Switching Characteristics for Programming OperationProgramming Operation of the 8702A Program OperationII. Programming of the 8702A Using Intel Microcomputers Operation of the 8702A in Program ModeIII a Erasing Procedure Programming Instructions for the 8702APage PIN Names PIN Configurations Block DiagramIII CommentIBB VOH1Test Conditions Symbol Parameter Typ. Max. Unit ConditionsWaveforms Max UnitTpF Program Pulse Fall Time Parameter MinProgramming Current RnA Program Pulse Amplitude CS/WE = +12V Read/Program/Read Transitions+-------1 PEEEf!1EJEZPlEzz$m=2!·m·· Icc 150 rSilicon Gate MOS MAX Unit CommentCS=O.O Outa100 ns 7001 JJ.s ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\200ns 500ns 300 ns Cs .. o.~ ~r Typical CharacteristicsSilicon Gate MOS Ilpc IlclIlkc ILOCoUT Conditions of Test for CharacteristicsCIN ~ ~ ~ Marking Mask Option SpecificationsPppp Customer Number OateTitle Card ~ r ------ + -- t --- . L . ------ rJBlank 79-80Intel Silicon Gate MOS ROM 8316A PIN Configuration Block DiagramConditions of Test for 400CAPACITANCE2 TA = 25C, f = 1 MHz Waveforms OU~TVALIDILICO.N Gate MOS ROM 8316A Typical D.C. CharacteristicsNumber Oate CustomerSTO Mask Option Speci FicationsCOM~ANY Name Title CardRAMs Page Silicon Gate MOS PIN Configuration Logic Symbol Block Diagram= OC ~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~=10H = -150 p.A +----+00 ~ Conditions of TestPage Silicon Gate MOS PIN Configuration Logic Symbol Block DiagramIII Symbol Parameter Min. Typ.rICC1 ICC2550 200 Write 1~-tAW--.I-----IInput Pulse Rise and Fall Times 20nsec Timing Measurement Reference Level VoltPage Silicon Gate MOS 5V to +7V Power Dissipation WattComment TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified+--~~~TL~~~EEt~~~P-.± 85o-·-···TCapacitance T a = 25C, f = 1MHz Conditions of Test~~~b~.J Typical A.C. CharacteristicsSilicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 230 450300 Access Time VS Ambient Temperature VIN Limits VS. TemperatureAccess Time VS LOAD·CAPACITANCE Output Source Current VSPIN Configuration Logic Symbol Block Diagram Fully Decoded Random Access BIT Dynamic MemoryIOOAV2 Silicon Gate MOS 81078·4IMP~ri~~CE II.~4000 Read CycleRef = Write CycleTypical Characteristics RWc 590 CD Symbol Parameter Min MaxNumbers in parentheses are for minimum cycle timing in ns Standby Power Power DissipationRefresh System Interfaces and FilteringTypical System BIT 256 x 4 Static Cmos RAM VIH VOL VOH ICC2VOR IcccrTiming Measurement Reference Level Volt Input Pulse Rise and Fall Times 20nsec~I----- t CW2 ------ . t Schottky Bipolar PIN Configuration Logic SymbolVoo- --- ---T Conditions of TestAll driver outputs are in the state indicated Power Supply Current Drain and Power DissipationTypical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page EIGHT-BIT INPUT/OUTPUT Port PIN Configuration Logic DiagramOS2 Functional DescriptionII. Gated Buffer 3·STATE Basic Schematic SymbolsAre 3-state Gated BufferIV. Interrupting Input Port III. Bi-Directional Bus DriverInterrupt Instruction Port BI-DIRECTIONAL BUS DriverVII Status Latch VI. Output Port With Hand-Shaking8080 4 OvJ \.. -4~OUT Viii SystemVee SystemIX System 1G~D L-~ DalN-t?!NrJAbsolute Maximum Ratings· Characteristics052 ~ Typical CharacteristicsTpw OUTTA = OC to + 75C Vee = +5V ± 5% Switching Characteristics12 pF ~~~lEI~S 1-- +SV Programmable Peripheral InterfaceData Bus Buffer GeneralRead/Write and Control Logic Basic Functional DescriptionPIN Configuration ResetGroup a and Group B Controls Ports A, B, and CSingle Bit Set/Reset Feature Mode SelectionDetailed Operational Description PA 7 ·pAoMode 0 Timing Operating Modes Mode 0 Basic Input/OutputInterrupt Control Functions Mode 0 Configurations Mode 0 Port Definition Chart119 · / ,4 Operating Modes Mode 1 Strobed Input/OutputIBF Input Buffer Full F/F Input Control Signal DefinitionIntr Interrupt Request Inte aIntea Output Control Signal DefinitionBi-Directional Bus I/O Control Signal Definition Combinations of ModeOperating Modes Output OperationsMode 2 Bi-directional Timing Mode 2 Control WordMode 2 and Mode 0 Output Mode 2 CombinationsMode Definition Summary Table Special Mode Combination ConsiderationsSource Current Capability on Port B and Port C Reading Port C StatusPrinter Interface ApplicationsKeyboard and Display Interface Keyboard and Terminal Address Interface~.LEFT/RIGHT PCOSilicon Gate MOS Vil Input Low Voltage Characteristics TA = oc to 70C Vee = +5V ±5% vss = OVInput High Voltage Val Output Low Voltage IOl = 1.6mA Time From STB = 0 To IBFMode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface General Reset ResetReadlWrite Control logic ClK ClockDSR Data Set Ready Modem ControlTxE Transmitter Empty DTR Data Termin·al ReadyReceiver Control Receiver BufferRxRDY Receiver Ready RxC Receiver ClockCommand Instruction Mode InstructionDetailed Operation Description ProgrammingAsynchronous Mode Transmission Mode Instruction DefinitionAsynchronous Mode Receive Data C~~RACTERSynchronous Mode Receive Synchronous Mode TransmissionMode Instruction Format, Synchronous Mode Synchronous Mode, Transmission FormatCommand Instruction Format Command Instruction DefinitionStatus Read Definition Status Read FormatAsynchronous Interface to Telephone Lines Asynchronous Serial Interface to CRT Terminal, DC-9600 BaudSynchronous Interface to Terminal or Peripheral Device Synchronous Interface to Telephone LinesIcc CapacitanceIOL Typ TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol ParameterSRX ~4IlI RxD~AST BIT ,----1 RXD~Peripherals Page High Speed 1 OUT of 8 Binary Decoder Decoder Enable GateSystem Port Decoder Using a very similar circuit to the I/O port decoder, an arChip Select Decoder 24K Memory Interface\lJ Logic Element ExampleJJ,.--+-I----.....1 IllTypical Characteristics Characteristics TA = OOC to +75C, Vee = 5.0V ±5%Symbol VOL VOH 8205Address or Enable to Output Delay VS. Load Capacitance Switching Characteristics Conditions of Test Test LoadAddress or Enable to Output Delay VS. Ambient Temperature Test Waveforms~ R PIN Configuration~ ~ Polled Method Interrupts in Microcomputer SystemsInterrupt Method Current Status Register Priority EncoderINTE, elK Control SignalsElR, ETlG, ENGl AO, A1, A2Basic Operation Level ControllerLevel Controller I ICascading Symbol Parameter Limits Unit Conditions Min Typ.£1 Operating CharacteristicsLos Absolute Maximum RatingsCharacteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar 8216 8226 +-......---- n csControl Gating OlEN, CS Bi-Directional DriverMemory and 1/0 Interface to a Bi-directional Bus Applications of 8216/8226Large microcomputer systems it is often necessary to pro Input Load Current OlEN, CS VF =0.45 IcC Power Supply Current 120Input Load Current All Other Inputs VF =0.45 Input Leakage Current OlEN, CS VR =5.25VOUT WaveformsPage 8253 8257 8259 Page It uses nMOS technology ~Jmodesof operation are Programmable Interval TimerPreliminary Functional Description Block DiagramSystem Interface System InterfaceProgrammable DMA Controller Dack 2 System InterfaceSystem Application CS-------It LJJ ROMs RAMs CPU GroupPeripheral Coming Soon Intel735~ ~~~1It-j ·34o~ \.--.J.. ~~~lLead Plastic Dual IN-LINE Package P Lead CerDIP Dual IN-LINE Package DSales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Summary of Processor Instructions By Alphabetical Order Instruction SETMicrocomputer System Users Registration Card Microcomputer Systems Bowers Avenue Santa Clara, CA Intel CorporationInter