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Intel 8080 manual ~I----- t CW2 ------ . t

Models: 8080

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SILICON GATE CMOS 5101,5101-3, 5101L, 5101L-3

Waveforms

	READ CYCLE ..--	_	WRITE CYCLE
	READ CYCLE ..--	_	1 .. ------- t we ------~
			1 .. ------- t we ------~
	ADDRESS		ADDRESS
			14 ----- t ew1 ---...

CE2CE2

	~I-----t CW2 ------ . t
00	00
(COMMON I/O) (3]	(COMMON I/O) (4)
	(COMMON I/O) (4)
DATA	DATA	DATA IN
OUT	IN	STABLE
		1 .. ---- tDw---~
	-- .	tAW 104 ---- t ---- . I ~__- +__
		wP

RIW

NOTES: 1. Typical values are for TA = 25° C and nominal supply voltage.

2.This parameter is periodically sampled and is not 100% tested.

3.00 may be tied low for separate I/O operation.

4.During the write cycle, 00 is "high" for common I/O and "don't care" for separate I/O operation.

Low VCC Data Retention

	DATA RETENTION
	MODE
SUPPLVVOLTAGE (Vee)	<D
	®
®	®
®	@
CHIP ENABLE (CE2) @	@

W ----------------

4.75V

VOR

VIH

O.2V

5-94

Image 160

Intel 8080 manual ~I----- t CW2 ------ . t

Contents

Page Clock Generator for 8080A System Controller for 8080AProgrammable Communication Interface Programmable Peripheral InterfaceContents Peri pherals 127Chapter Packaging Information Page Microcomputer Design Aids Advantages of Designing With MicrocomputersConventional System Programmed Logic Iii Applications Example1IIII~Iff1 Application Peripheral Devices EncounteredArchitecture of a CPU Typical Computer SystemAccumulator Program Counter Jumps, Subroutines and the Stack Instruction Register and DecoderControl Circuitry Address RegistersArithmetic/Logic Unit ALU Computer OperationsInstruction Fetch Memory ReadMemory Write Wait memory synchronizationPage Page INTE~ 8080 Photomicrograph With Pin DesignationsArchitecture of the 8080 CPU RegistersArithmetic and Logic Unit ALU Instruction Register and ControlData Bus Buffer Processor CycleMachine Cycle Identification State Transition Sequence HaltStatus Bit Definitions Status Word ChartStatus Information Definition CPU State Transition Diagram ?~~Rr\ ONE ,----- ~ State Associated Activities ~2. State DefinitionsRLrL- rL rL rL-rL- rLrL Interrupt Sequences¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL Halt Sequences Hold SequencesSTART-UP of the 8080 CPU 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~iA~~~11 ~iA~~ll,12~A~~~ll ~iA~~~11Value 111 000 001 010 011 100 101Typical Computer System Block Diagram Basic System OperationCPU Module Design 8080 CPUClock Generator and High Level Driver Clock Generator Design~50ns ClK 0.......-..-.-----.. tf1A TTLHigh Level Driver Design Ststb !1 Page ROM Interface Interfacing the 8080 CPU to Memory and I/O DevicesRAM Interface Ill Interface General TheoryIsolated I/O Memory Mapped I/OInterface Example AddressingMemr to 13 Format 15 FormatInstruction and Data Formats 8080 Instruction SETByte One Byte TwoByte Three I D7 Addressing ModesSymbols and Abbreviations Symbols MeaningDescription Format AllContent of register r2 is moved to register r1 Data Transfer GroupMOV r1, r2 Move Register Reg. indirect0 I R p 0 I R0 I Arithmetic Group1 I 0 I 0 oR 0 I 0 I D I DI I Logical GroupOCR M Decrement memory Cycles States Addressing reg. indirect Flags Z,S,P ,CY,ACI 0 I 1 I 1 I I 1 I 1 o I 1 I 1 I~11~ 1 1 10 I 1 I 0 I 0 1 I0 I 0 I Cycles States Flags noneBranch Group 000Ccondition addr I c c I c I 0 I 0 ISP ~ SP + Stack, I/O, and Machine Control Group I 1 oPush rp 1 I RExchange stack top with Hand L ~ SP +~ data Cycles States Flags NoneInstruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page Schottky Bipolar PIN NamesFunctional Description GeneralOscillator Clock GeneratorPower-On Reset and Ready Flip-Flops Ststb Status StrobeCharacteristics Crystal RequirementsInput 8pFCharacteristics For tCY = 488.28 ns ExampleT42 T01 T02 T03 Toss TORS tORH tOR FMAXPIN Configuration Block Diagram DbinGeneral BlockSignals Inta None ControlCharacteristics TA = Oc to 70C Vee = 5V ±5% TE~rWaveforms Hlda to Read Status OutputsGoUT StstbVTH VCC=5V·-c GND ---. rIntel Silicon Gate MOS 8080 a ?oo .HVss Vee8080A Functional PIN Definition Characteristics Absolute Maximum RATINGS·Capacitance IOl = 1.9mA on all outputs=..... -r-DATAIN ~I~~~Timing Waveforms ~~1 t CYCharacteristics Typical ~ Output Delay VS. a CapacitanceInstruction SET Typical InstructionsSilicon Gate MOS 8080.A Summary of Processor InstructionsInfel Silicon Gate MOS 8080A-1 Max Symbol Parameter TypUnit ~tOF.I Fft~l~-t TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 +10 CoutJ1A VAOOR/OATA = VSS + O.45VSymbol Parameter Min Unit Test ConditionTypical ~ Output Delay VS. ~ Capacitance Min. Max. Unit Test ConditionPage Intel . Silicon Gate MOS M8080A Immediate mode or I/O instructions Register to regist~r, memory referEnce, arithmetic or logical, rotate Interrupt instructionsSummary of Processor Instructions Llf17Silicon Gate MOS M8080A M8080A Functional PIN DefinitionIOL = 1.9mA on all outputs Absolute Maximum RatingsOperation Symbol Parameter Min. Max Unit Test Condition Silicon Gate MOS M8080A ~I~Page ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A PIN Connections Operating CharacteristicsVoo Switching Characteristics 1N= Vee~10% = V ce\ \ Cs=o.~Operating Characteristics for Programming Operation Symbol TestCharacteristics for Programming Operation SYMBOLTESTMIN. TYP. MAX. Unit ConditionsSwitching Characteristics for Programming Operation CS = OVProgramming Operation of the 8702A Program OperationOperation of the 8702A in Program Mode II. Programming of the 8702A Using Intel MicrocomputersIII a Erasing Procedure Programming Instructions for the 8702APage PIN Configurations Block Diagram PIN NamesComment IIIIBB VOH1Symbol Parameter Typ. Max. Unit Conditions Test ConditionsWaveforms Max UnitTpF Program Pulse Fall Time Parameter MinProgramming Current RnA Program Pulse Amplitude CS/WE = +12V Read/Program/Read Transitions+-------1 150 r PEEEf!1EJEZPlEzz$m=2!·m·· IccSilicon Gate MOS Comment MAX UnitCS=O.O Outa100 ns 7001 JJ.s ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\200ns 500ns 300 ns Typical Characteristics Cs .. o.~ ~rSilicon Gate MOS Ilcl IlpcIlkc ILOCoUT Conditions of Test for CharacteristicsCIN ~ ~ ~ Mask Option Specifications MarkingPppp Customer Number Oate~ r ------ + -- t --- . L . ------ rJ Title CardBlank 79-80PIN Configuration Block Diagram Intel Silicon Gate MOS ROM 8316AConditions of Test for 400CAPACITANCE2 TA = 25C, f = 1 MHz OU~TVALID WaveformsTypical D.C. Characteristics ILICO.N Gate MOS ROM 8316ACustomer Number OateSTO Mask Option Speci FicationsTitle Card COM~ANY NameRAMs Page PIN Configuration Logic Symbol Block Diagram Silicon Gate MOS~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~= = OC10H = -150 p.A +----+Conditions of Test 00 ~Page PIN Configuration Logic Symbol Block Diagram Silicon Gate MOSSymbol Parameter Min. Typ.r IIIICC1 ICC2Write 1~-tAW--.I-----I 550 200Input Pulse Rise and Fall Times 20nsec Timing Measurement Reference Level VoltPage Silicon Gate MOS Power Dissipation Watt 5V to +7VComment TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified85o-·-···T +--~~~TL~~~EEt~~~P-.±Capacitance T a = 25C, f = 1MHz Conditions of TestTypical A.C. Characteristics ~~~b~.JSilicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 230 450300 VIN Limits VS. Temperature Access Time VS Ambient TemperatureAccess Time VS LOAD·CAPACITANCE Output Source Current VSFully Decoded Random Access BIT Dynamic Memory PIN Configuration Logic Symbol Block DiagramSilicon Gate MOS 81078·4 IOOAV2II.~ IMP~ri~~CERead Cycle 4000Ref = Write CycleTypical Characteristics RWc 590 CD Symbol Parameter Min MaxNumbers in parentheses are for minimum cycle timing in ns Power Dissipation Standby PowerRefresh System Interfaces and FilteringTypical System BIT 256 x 4 Static Cmos RAM ICC2 VIH VOL VOHVOR IcccrInput Pulse Rise and Fall Times 20nsec Timing Measurement Reference Level Volt~I----- t CW2 ------ . t PIN Configuration Logic Symbol Schottky BipolarConditions of Test Voo- --- ---TPower Supply Current Drain and Power Dissipation All driver outputs are in the state indicatedTypical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page PIN Configuration Logic Diagram EIGHT-BIT INPUT/OUTPUT PortFunctional Description OS2Basic Schematic Symbols II. Gated Buffer 3·STATEAre 3-state Gated BufferIII. Bi-Directional Bus Driver IV. Interrupting Input PortInterrupt Instruction Port BI-DIRECTIONAL BUS DriverVI. Output Port With Hand-Shaking VII Status Latch8080 4 OvJ \.. -4~Viii System OUTVee SystemIX System DalN-t?!NrJ 1G~D L-~Characteristics Absolute Maximum Ratings·Typical Characteristics 052 ~OUT TpwTA = OC to + 75C Vee = +5V ± 5% Switching Characteristics12 pF Programmable Peripheral Interface ~~~lEI~S 1-- +SVGeneral Data Bus BufferRead/Write and Control Logic Basic Functional DescriptionReset PIN ConfigurationGroup a and Group B Controls Ports A, B, and CMode Selection Single Bit Set/Reset FeatureDetailed Operational Description PA 7 ·pAoMode 0 Timing Operating Modes Mode 0 Basic Input/OutputInterrupt Control Functions Mode 0 Port Definition Chart Mode 0 Configurations119 Operating Modes Mode 1 Strobed Input/Output · / ,4Input Control Signal Definition IBF Input Buffer Full F/FIntr Interrupt Request Inte aOutput Control Signal Definition InteaCombinations of Mode Bi-Directional Bus I/O Control Signal DefinitionOperating Modes Output OperationsMode 2 Control Word Mode 2 Bi-directional TimingMode 2 Combinations Mode 2 and Mode 0 OutputSpecial Mode Combination Considerations Mode Definition Summary TableSource Current Capability on Port B and Port C Reading Port C StatusApplications Printer InterfaceKeyboard and Display Interface Keyboard and Terminal Address InterfacePCO ~.LEFT/RIGHTSilicon Gate MOS Characteristics TA = oc to 70C Vee = +5V ±5% vss = OV Vil Input Low VoltageInput High Voltage Val Output Low Voltage IOl = 1.6mA Time From STB = 0 To IBFMode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface Reset Reset GeneralReadlWrite Control logic ClK ClockModem Control DSR Data Set ReadyTxE Transmitter Empty DTR Data Termin·al ReadyReceiver Buffer Receiver ControlRxRDY Receiver Ready RxC Receiver ClockMode Instruction Command InstructionDetailed Operation Description ProgrammingMode Instruction Definition Asynchronous Mode TransmissionAsynchronous Mode Receive Data C~~RACTERSynchronous Mode Transmission Synchronous Mode ReceiveMode Instruction Format, Synchronous Mode Synchronous Mode, Transmission FormatCommand Instruction Definition Command Instruction FormatStatus Read Definition Status Read FormatAsynchronous Serial Interface to CRT Terminal, DC-9600 Baud Asynchronous Interface to Telephone LinesSynchronous Interface to Terminal or Peripheral Device Synchronous Interface to Telephone LinesIcc CapacitanceIOL TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol Parameter TypRxD SRX ~4IlI~AST BIT ,----1 RXD~Peripherals Page High Speed 1 OUT of 8 Binary Decoder Decoder Enable GateSystem Using a very similar circuit to the I/O port decoder, an ar Port DecoderChip Select Decoder 24K Memory InterfaceLogic Element Example \lJJJ,.--+-I----.....1 IllCharacteristics TA = OOC to +75C, Vee = 5.0V ±5% Typical CharacteristicsSymbol VOL VOH 8205Switching Characteristics Conditions of Test Test Load Address or Enable to Output Delay VS. Load CapacitanceAddress or Enable to Output Delay VS. Ambient Temperature Test Waveforms~ R PIN Configuration~ ~ Polled Method Interrupts in Microcomputer SystemsInterrupt Method Priority Encoder Current Status RegisterControl Signals INTE, elKElR, ETlG, ENGl AO, A1, A2Level Controller Basic OperationI I Level ControllerCascading Operating Characteristics Symbol Parameter Limits Unit Conditions Min Typ.£1Los Absolute Maximum RatingsCharacteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar +-......---- n cs 8216 8226Bi-Directional Driver Control Gating OlEN, CSMemory and 1/0 Interface to a Bi-directional Bus Applications of 8216/8226Large microcomputer systems it is often necessary to pro IcC Power Supply Current 120 Input Load Current OlEN, CS VF =0.45Input Load Current All Other Inputs VF =0.45 Input Leakage Current OlEN, CS VR =5.25VWaveforms OUTPage 8253 8257 8259 Page Programmable Interval Timer It uses nMOS technology ~Jmodesof operation areBlock Diagram Preliminary Functional DescriptionSystem Interface System InterfaceProgrammable DMA Controller Dack 2 System InterfaceSystem Application CS-------It LJJ CPU Group ROMs RAMsPeripheral Coming Soon Intel735~ ~~~1It-j \.--.J.. ~~~l ·34o~Lead Plastic Dual IN-LINE Package P Lead CerDIP Dual IN-LINE Package DSales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Instruction SET Summary of Processor Instructions By Alphabetical OrderMicrocomputer System Users Registration Card Intel Corporation Microcomputer Systems Bowers Avenue Santa Clara, CAInter