Page
 System Controller for 8080A
Clock Generator for 8080A
Programmable Communication Interface
Programmable Peripheral Interface
 Contents
 127
Peri pherals
Chapter Packaging Information
Page
 Advantages of Designing With Microcomputers
Microcomputer Design Aids
Conventional System Programmed Logic
 Applications Example
Iii
1IIII~Iff1
 Peripheral Devices Encountered
Application
 Typical Computer System
Architecture of a CPU
Accumulator
 Instruction Register and Decoder
Program Counter Jumps, Subroutines and the Stack
 Address Registers
Control Circuitry
Arithmetic/Logic Unit ALU
Computer Operations
 Memory Read
Instruction Fetch
Memory Write
Wait memory synchronization
Page
Page
 8080 Photomicrograph With Pin Designations
INTE~
 Registers
Architecture of the 8080 CPU
 Instruction Register and Control
Arithmetic and Logic Unit ALU
Data Bus Buffer
Processor Cycle
 Machine Cycle Identification
 Halt
State Transition Sequence
 Status Word Chart
Status Bit Definitions
Status Information Definition
 ?~~
CPU State Transition Diagram
 Rr\
 ONE ,----- ~
 ~2. State Definitions
State Associated Activities
 Interrupt Sequences
RLrL- rL rL rL-rL- rLrL
 ¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL
 Hold Sequences
Halt Sequences
START-UP of the 8080 CPU
 11. Halt Timing
 ~~~~t==p
 001
 STATUS6
 Xram
 ~iA~~ll,12
~iA~~~11
~A~~~ll
~iA~~~11
 111 000 001 010 011 100 101
Value
 Basic System Operation
Typical Computer System Block Diagram
 8080 CPU
CPU Module Design
Clock Generator and High Level Driver
Clock Generator Design
 ClK 0.......-..-.-----.. tf1A TTL
~50ns
High Level Driver Design
 Ststb !1
Page
 Interfacing the 8080 CPU to Memory and I/O Devices
ROM Interface
RAM Interface
 Ill
 General Theory
Interface
Isolated I/O
Memory Mapped I/O
 Addressing
Interface Example
Memr to
 15 Format
13 Format
 8080 Instruction SET
Instruction and Data Formats
 Byte Two
Byte One
Byte Three I D7
Addressing Modes
 Symbols Meaning
Symbols and Abbreviations
Description Format
All
 Data Transfer Group
Content of register r2 is moved to register r1
MOV r1, r2 Move Register
Reg. indirect
 0 I R
0 I R p
 Arithmetic Group
0 I
1 I
0 I 0 o
 0 I D I D
R 0 I
 Logical Group
I I
OCR M Decrement memory
Cycles States Addressing reg. indirect Flags Z,S,P ,CY,AC
 I 1 I 1 o I 1 I 1 I
I 0 I 1 I 1 I
~11~
1 1 1
 0 I 0 1 I
0 I 1 I
0 I 0 I
Cycles States Flags none
 000
Branch Group
 I c c I c I 0 I 0 I
Ccondition addr
SP ~ SP +
 I 1 o
Stack, I/O, and Machine Control Group
Push rp
1 I R
 ~ SP +
Exchange stack top with Hand L
~ data
Cycles States Flags None
 Instruction SET
 Programmable Peripheral Interface
 8224 8080A-1 8228 8080A-2 8080A M8080-A
Page
 PIN Names
Schottky Bipolar
 General
Functional Description
Oscillator
Clock Generator
 Ststb Status Strobe
Power-On Reset and Ready Flip-Flops
 Crystal Requirements
Characteristics
 8pF
Input
 Example
Characteristics For tCY = 488.28 ns
T42 T01 T02 T03 Toss
TORS tORH tOR FMAX
 Dbin
PIN Configuration Block Diagram
 Block
General
 Inta None Control
Signals
 TE~r
Characteristics TA = Oc to 70C Vee = 5V ±5%
Waveforms
Hlda to Read Status Outputs
 Ststb
GoUT
VTH
VCC=5V
 GND ---. r
·-c
 ?oo .H
Intel Silicon Gate MOS 8080 a
 Vee
Vss
8080A Functional PIN Definition
 Absolute Maximum RATINGS·
Characteristics
Capacitance
IOl = 1.9mA on all outputs
 ~I~~~
=..... -r-DATAIN
Timing Waveforms
~~1 t CY
 Typical ~ Output Delay VS. a Capacitance
Characteristics
 Typical Instructions
Instruction SET
 Summary of Processor Instructions
Silicon Gate MOS 8080.A
 Infel Silicon Gate MOS 8080A-1
 Symbol Parameter Typ
Max
Unit
 Fft~l
~tOF.I
~-t
 TYPICAL!J. Output Delay VS. ~ Capacitance
 Infel Silicon Gate MOS 8080 A-2
 Cout
+10
J1A
VAOOR/OATA = VSS + O.45V
 Unit Test Condition
Symbol Parameter Min
 Min. Max. Unit Test Condition
Typical ~ Output Delay VS. ~ Capacitance
Page
 Intel . Silicon Gate MOS M8080A
 Register to regist~r, memory refer
Immediate mode or I/O instructions
Ence, arithmetic or logical, rotate
Interrupt instructions
 Llf17
Summary of Processor Instructions
 M8080A Functional PIN Definition
Silicon Gate MOS M8080A
 Absolute Maximum Ratings
IOL = 1.9mA on all outputs
Operation
 Symbol Parameter Min. Max Unit Test Condition
 ~I~
Silicon Gate MOS M8080A
Page
 ROMs 8702A 8704 8708 8316A
Page
 Silicon Gate MOS 8702A
 Operating Characteristics
PIN Connections
Voo
 1N= Vee
Switching Characteristics
~10%
= V ce
 Cs=o.~
\ \
 Symbol Test
Operating Characteristics for Programming Operation
Characteristics for Programming Operation
SYMBOLTESTMIN. TYP. MAX. Unit Conditions
 CS = OV
Switching Characteristics for Programming Operation
Programming Operation of the 8702A
Program Operation
 II. Programming of the 8702A Using Intel Microcomputers
Operation of the 8702A in Program Mode
III a Erasing Procedure
Programming Instructions for the 8702A
Page
 PIN Names
PIN Configurations Block Diagram
 III
Comment
IBB
VOH1
 Test Conditions
Symbol Parameter Typ. Max. Unit Conditions
Waveforms
Max Unit
 Parameter Min
TpF Program Pulse Fall Time
Programming Current RnA Program Pulse Amplitude
 Read/Program/Read Transitions
CS/WE = +12V
+-------1
 PEEEf!1EJEZPlEzz$m=2!·m·· Icc
150 r
 Silicon Gate MOS
 MAX Unit
Comment
CS=O.O
Outa
 ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\
100 ns 7001 JJ.s
200ns 500ns 300 ns
 Cs .. o.~ ~r
Typical Characteristics
 Silicon Gate MOS
 Ilpc
Ilcl
Ilkc
ILO
 Conditions of Test for Characteristics
CoUT
CIN
 ~ ~ ~
 Marking
Mask Option Specifications
Pppp
Customer Number Oate
 Title Card
~ r ------ + -- t --- . L . ------ rJ
Blank
79-80
 Intel Silicon Gate MOS ROM 8316A
PIN Configuration Block Diagram
 400
Conditions of Test for
CAPACITANCE2 TA = 25C, f = 1 MHz
 Waveforms
OU~TVALID
 ILICO.N Gate MOS ROM 8316A
Typical D.C. Characteristics
 Number Oate
Customer
STO
Mask Option Speci Fications
 COM~ANY Name
Title Card
 RAMs
Page
 Silicon Gate MOS
PIN Configuration Logic Symbol Block Diagram
 = OC
~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~=
10H = -150 p.A
+----+
 00 ~
Conditions of Test
Page
 Silicon Gate MOS
PIN Configuration Logic Symbol Block Diagram
 III
Symbol Parameter Min. Typ.r
ICC1
ICC2
 550 200
Write 1~-tAW--.I-----I
Input Pulse Rise and Fall Times 20nsec
Timing Measurement Reference Level Volt
Page
 Silicon Gate MOS
 5V to +7V
Power Dissipation Watt
Comment
TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified
 +--~~~TL~~~EEt~~~P-.±
85o-·-···T
Capacitance T a = 25C, f = 1MHz
Conditions of Test
 ~~~b~.J
Typical A.C. Characteristics
 Silicon Gate MOS 8102A-4
 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified
 450
230
300
 Access Time VS Ambient Temperature
VIN Limits VS. Temperature
Access Time VS LOAD·CAPACITANCE
Output Source Current VS
 PIN Configuration Logic Symbol Block Diagram
Fully Decoded Random Access BIT Dynamic Memory
 IOOAV2
Silicon Gate MOS 81078·4
 IMP~ri~~CE
II.~
 4000
Read Cycle
Ref =
Write Cycle
 Typical Characteristics
 Symbol Parameter Min Max
RWc 590 CD
Numbers in parentheses are for minimum cycle timing in ns
 Standby Power
Power Dissipation
Refresh
System Interfaces and Filtering
 Typical System
 BIT 256 x 4 Static Cmos RAM
 VIH VOL VOH
ICC2
VOR
Icccr
 Timing Measurement Reference Level Volt
Input Pulse Rise and Fall Times 20nsec
 ~I----- t CW2 ------ . t
 Schottky Bipolar
PIN Configuration Logic Symbol
 Voo- --- ---T
Conditions of Test
 All driver outputs are in the state indicated
Power Supply Current Drain and Power Dissipation
 Typical System
 Dynamic Memory Refresh Controller
Page
 8212 8255 8251
Page
 EIGHT-BIT INPUT/OUTPUT Port
PIN Configuration Logic Diagram
 OS2
Functional Description
 II. Gated Buffer 3·STATE
Basic Schematic Symbols
Are 3-state
Gated Buffer
 IV. Interrupting Input Port
III. Bi-Directional Bus Driver
Interrupt Instruction Port
BI-DIRECTIONAL BUS Driver
 VII Status Latch
VI. Output Port With Hand-Shaking
8080 4
OvJ \.. -4~
 OUT
Viii System
Vee
System
 IX System
 1G~D L-~
DalN-t?!NrJ
 Absolute Maximum Ratings·
Characteristics
 052 ~
Typical Characteristics
 Tpw
OUT
 Switching Characteristics
TA = OC to + 75C Vee = +5V ± 5%
12 pF
 ~~~lEI~S 1-- +SV
Programmable Peripheral Interface
 Data Bus Buffer
General
Read/Write and Control Logic
Basic Functional Description
 PIN Configuration
Reset
Group a and Group B Controls
Ports A, B, and C
 Single Bit Set/Reset Feature
Mode Selection
Detailed Operational Description
PA 7 ·pAo
 Operating Modes Mode 0 Basic Input/Output
Mode 0 Timing
Interrupt Control Functions
 Mode 0 Configurations
Mode 0 Port Definition Chart
 119
 · / ,4
Operating Modes Mode 1 Strobed Input/Output
 IBF Input Buffer Full F/F
Input Control Signal Definition
Intr Interrupt Request
Inte a
 Intea
Output Control Signal Definition
 Bi-Directional Bus I/O Control Signal Definition
Combinations of Mode
Operating Modes
Output Operations
 Mode 2 Bi-directional Timing
Mode 2 Control Word
 Mode 2 and Mode 0 Output
Mode 2 Combinations
 Mode Definition Summary Table
Special Mode Combination Considerations
Source Current Capability on Port B and Port C
Reading Port C Status
 Printer Interface
Applications
Keyboard and Display Interface
Keyboard and Terminal Address Interface
 ~.LEFT/RIGHT
PCO
 Silicon Gate MOS
 Vil Input Low Voltage
Characteristics TA = oc to 70C Vee = +5V ±5% vss = OV
Input High Voltage Val Output Low Voltage IOl = 1.6mA
Time From STB = 0 To IBF
 Mode 0 Basic Input
 Mode 1 Strobed Input
 Mode 2 Bi-directional
Page
 Programmable Communication Interface
 General
Reset Reset
ReadlWrite Control logic
ClK Clock
 DSR Data Set Ready
Modem Control
TxE Transmitter Empty
DTR Data Termin·al Ready
 Receiver Control
Receiver Buffer
RxRDY Receiver Ready
RxC Receiver Clock
 Command Instruction
Mode Instruction
Detailed Operation Description
Programming
 Asynchronous Mode Transmission
Mode Instruction Definition
Asynchronous Mode Receive
Data C~~RACTER
 Synchronous Mode Receive
Synchronous Mode Transmission
Mode Instruction Format, Synchronous Mode
Synchronous Mode, Transmission Format
 Command Instruction Format
Command Instruction Definition
Status Read Definition
Status Read Format
 Asynchronous Interface to Telephone Lines
Asynchronous Serial Interface to CRT Terminal, DC-9600 Baud
Synchronous Interface to Terminal or Peripheral Device
Synchronous Interface to Telephone Lines
 Capacitance
Icc
IOL
 Typ
TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol Parameter
 SRX ~4IlI
RxD
~AST BIT ,----1
RXD~
 Peripherals
Page
 High Speed 1 OUT of 8 Binary Decoder
 Enable Gate
Decoder
System
 Port Decoder
Using a very similar circuit to the I/O port decoder, an ar
Chip Select Decoder
24K Memory Interface
 \lJ
Logic Element Example
JJ,.--+-I----.....1
Ill
 Typical Characteristics
Characteristics TA = OOC to +75C, Vee = 5.0V ±5%
Symbol VOL VOH
8205
 Address or Enable to Output Delay VS. Load Capacitance
Switching Characteristics Conditions of Test Test Load
Address or Enable to Output Delay VS. Ambient Temperature
Test Waveforms
 PIN Configuration
~ R
~ ~
 Interrupts in Microcomputer Systems
Polled Method
Interrupt Method
 Current Status Register
Priority Encoder
 INTE, elK
Control Signals
ElR, ETlG, ENGl
AO, A1, A2
 Basic Operation
Level Controller
 Level Controller
I I
 Cascading
 Symbol Parameter Limits Unit Conditions Min Typ.£1
Operating Characteristics
Los
Absolute Maximum Ratings
 Characteristics and Waveforms TA = oc to +70C, vcc = +5V ±5%
 Schottky Bipolar
 8216 8226
+-......---- n cs
 Control Gating OlEN, CS
Bi-Directional Driver
 Applications of 8216/8226
Memory and 1/0 Interface to a Bi-directional Bus
Large microcomputer systems it is often necessary to pro
 Input Load Current OlEN, CS VF =0.45
IcC Power Supply Current 120
Input Load Current All Other Inputs VF =0.45
Input Leakage Current OlEN, CS VR =5.25V
 OUT
Waveforms
Page
 8253 8257 8259
Page
 It uses nMOS technology ~Jmodesof operation are
Programmable Interval Timer
 Preliminary Functional Description
Block Diagram
System Interface
System Interface
 Programmable DMA Controller
 System Interface
Dack 2
System Application
 CS-------It
 LJJ
 ROMs RAMs
CPU Group
Peripheral Coming Soon
Intel
 ~~~1
735~
It-j
 ·34o~
\.--.J.. ~~~l
Lead Plastic Dual IN-LINE Package P
Lead CerDIP Dual IN-LINE Package D
 Sales and Marketing Offices
 Distributors
Page
Page
Page
Page
Page
Page
 Instruction SET
 Summary of Processor Instructions By Alphabetical Order
Instruction SET
 Microcomputer System Users Registration Card
 Microcomputer Systems Bowers Avenue Santa Clara, CA
Intel Corporation
 Inter