Page
 Clock Generator for 8080A
System Controller for 8080A
Programmable Communication Interface
Programmable Peripheral Interface
 Contents
 127
Peri pherals
Chapter Packaging Information
Page
 Advantages of Designing With Microcomputers
Microcomputer Design Aids
Conventional System Programmed Logic
 Applications Example
Iii
1IIII~Iff1
 Application
Peripheral Devices Encountered
 Typical Computer System
Architecture of a CPU
Accumulator
 Program Counter Jumps, Subroutines and the Stack
Instruction Register and Decoder
 Control Circuitry
Address Registers
Arithmetic/Logic Unit ALU
Computer Operations
 Instruction Fetch
Memory Read
Memory Write
Wait memory synchronization
Page
Page
 INTE~
8080 Photomicrograph With Pin Designations
 Architecture of the 8080 CPU
Registers
 Arithmetic and Logic Unit ALU
Instruction Register and Control
Data Bus Buffer
Processor Cycle
 Machine Cycle Identification
 State Transition Sequence
Halt
 Status Word Chart
Status Bit Definitions
Status Information Definition
 CPU State Transition Diagram
?~~
 Rr\
 ONE ,----- ~
 State Associated Activities
~2. State Definitions
 RLrL- rL rL rL-rL- rLrL
Interrupt Sequences
 ¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL
 Hold Sequences
Halt Sequences
START-UP of the 8080 CPU
 11. Halt Timing
 ~~~~t==p
 001
 STATUS6
 Xram
 ~iA~~~11
~iA~~ll,12
~A~~~ll
~iA~~~11
 Value
111 000 001 010 011 100 101
 Typical Computer System Block Diagram
Basic System Operation
 CPU Module Design
8080 CPU
Clock Generator and High Level Driver
Clock Generator Design
 ClK 0.......-..-.-----.. tf1A TTL
~50ns
High Level Driver Design
 Ststb !1
Page
 Interfacing the 8080 CPU to Memory and I/O Devices
ROM Interface
RAM Interface
 Ill
 Interface
General Theory
Isolated I/O
Memory Mapped I/O
 Addressing
Interface Example
Memr to
 13 Format
15 Format
 Instruction and Data Formats
8080 Instruction SET
 Byte One
Byte Two
Byte Three I D7
Addressing Modes
 Symbols and Abbreviations
Symbols Meaning
Description Format
All
 Content of register r2 is moved to register r1
Data Transfer Group
MOV r1, r2 Move Register
Reg. indirect
 0 I R p
0 I R
 0 I
Arithmetic Group
1 I
0 I 0 o
 R 0 I
0 I D I D
 I I
Logical Group
OCR M Decrement memory
Cycles States Addressing reg. indirect Flags Z,S,P ,CY,AC
 I 0 I 1 I 1 I
I 1 I 1 o I 1 I 1 I
~11~
1 1 1
 0 I 1 I
0 I 0 1 I
0 I 0 I
Cycles States Flags none
 Branch Group
000
 I c c I c I 0 I 0 I
Ccondition addr
SP ~ SP +
 Stack, I/O, and Machine Control Group
I 1 o
Push rp
1 I R
 Exchange stack top with Hand L
~ SP +
~ data
Cycles States Flags None
 Instruction SET
 Programmable Peripheral Interface
 8224 8080A-1 8228 8080A-2 8080A M8080-A
Page
 Schottky Bipolar
PIN Names
 Functional Description
General
Oscillator
Clock Generator
 Power-On Reset and Ready Flip-Flops
Ststb Status Strobe
 Characteristics
Crystal Requirements
 Input
8pF
 Characteristics For tCY = 488.28 ns
Example
T42 T01 T02 T03 Toss
TORS tORH tOR FMAX
 PIN Configuration Block Diagram
Dbin
 General
Block
 Signals
Inta None Control
 Characteristics TA = Oc to 70C Vee = 5V ±5%
TE~r
Waveforms
Hlda to Read Status Outputs
 GoUT
Ststb
VTH
VCC=5V
 ·-c
GND ---. r
 Intel Silicon Gate MOS 8080 a
?oo .H
 Vee
Vss
8080A Functional PIN Definition
 Characteristics
Absolute Maximum RATINGS·
Capacitance
IOl = 1.9mA on all outputs
 =..... -r-DATAIN
~I~~~
Timing Waveforms
~~1 t CY
 Characteristics
Typical ~ Output Delay VS. a Capacitance
 Instruction SET
Typical Instructions
 Silicon Gate MOS 8080.A
Summary of Processor Instructions
 Infel Silicon Gate MOS 8080A-1
 Symbol Parameter Typ
Max
Unit
 Fft~l
~tOF.I
~-t
 TYPICAL!J. Output Delay VS. ~ Capacitance
 Infel Silicon Gate MOS 8080 A-2
 +10
Cout
J1A
VAOOR/OATA = VSS + O.45V
 Symbol Parameter Min
Unit Test Condition
 Typical ~ Output Delay VS. ~ Capacitance
Min. Max. Unit Test Condition
Page
 Intel . Silicon Gate MOS M8080A
 Immediate mode or I/O instructions
Register to regist~r, memory refer
Ence, arithmetic or logical, rotate
Interrupt instructions
 Summary of Processor Instructions
Llf17
 Silicon Gate MOS M8080A
M8080A Functional PIN Definition
 Absolute Maximum Ratings
IOL = 1.9mA on all outputs
Operation
 Symbol Parameter Min. Max Unit Test Condition
 Silicon Gate MOS M8080A
~I~
Page
 ROMs 8702A 8704 8708 8316A
Page
 Silicon Gate MOS 8702A
 Operating Characteristics
PIN Connections
Voo
 Switching Characteristics
1N= Vee
~10%
= V ce
 \ \
Cs=o.~
 Operating Characteristics for Programming Operation
Symbol Test
Characteristics for Programming Operation
SYMBOLTESTMIN. TYP. MAX. Unit Conditions
 Switching Characteristics for Programming Operation
CS = OV
Programming Operation of the 8702A
Program Operation
 Operation of the 8702A in Program Mode
II. Programming of the 8702A Using Intel Microcomputers
III a Erasing Procedure
Programming Instructions for the 8702A
Page
 PIN Configurations Block Diagram
PIN Names
 Comment
III
IBB
VOH1
 Symbol Parameter Typ. Max. Unit Conditions
Test Conditions
Waveforms
Max Unit
 Parameter Min
TpF Program Pulse Fall Time
Programming Current RnA Program Pulse Amplitude
 Read/Program/Read Transitions
CS/WE = +12V
+-------1
 150 r
PEEEf!1EJEZPlEzz$m=2!·m·· Icc
 Silicon Gate MOS
 Comment
MAX Unit
CS=O.O
Outa
 ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\
100 ns 7001 JJ.s
200ns 500ns 300 ns
 Typical Characteristics
Cs .. o.~ ~r
 Silicon Gate MOS
 Ilcl
Ilpc
Ilkc
ILO
 Conditions of Test for Characteristics
CoUT
CIN
 ~ ~ ~
 Mask Option Specifications
Marking
Pppp
Customer Number Oate
 ~ r ------ + -- t --- . L . ------ rJ
Title Card
Blank
79-80
 PIN Configuration Block Diagram
Intel Silicon Gate MOS ROM 8316A
 400
Conditions of Test for
CAPACITANCE2 TA = 25C, f = 1 MHz
 OU~TVALID
Waveforms
 Typical D.C. Characteristics
ILICO.N Gate MOS ROM 8316A
 Customer
Number Oate
STO
Mask Option Speci Fications
 Title Card
COM~ANY Name
 RAMs
Page
 PIN Configuration Logic Symbol Block Diagram
Silicon Gate MOS
 ~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~=
= OC
10H = -150 p.A
+----+
 Conditions of Test
00 ~
Page
 PIN Configuration Logic Symbol Block Diagram
Silicon Gate MOS
 Symbol Parameter Min. Typ.r
III
ICC1
ICC2
 Write 1~-tAW--.I-----I
550 200
Input Pulse Rise and Fall Times 20nsec
Timing Measurement Reference Level Volt
Page
 Silicon Gate MOS
 Power Dissipation Watt
5V to +7V
Comment
TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified
 85o-·-···T
+--~~~TL~~~EEt~~~P-.±
Capacitance T a = 25C, f = 1MHz
Conditions of Test
 Typical A.C. Characteristics
~~~b~.J
 Silicon Gate MOS 8102A-4
 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified
 450
230
300
 VIN Limits VS. Temperature
Access Time VS Ambient Temperature
Access Time VS LOAD·CAPACITANCE
Output Source Current VS
 Fully Decoded Random Access BIT Dynamic Memory
PIN Configuration Logic Symbol Block Diagram
 Silicon Gate MOS 81078·4
IOOAV2
 II.~
IMP~ri~~CE
 Read Cycle
4000
Ref =
Write Cycle
 Typical Characteristics
 Symbol Parameter Min Max
RWc 590 CD
Numbers in parentheses are for minimum cycle timing in ns
 Power Dissipation
Standby Power
Refresh
System Interfaces and Filtering
 Typical System
 BIT 256 x 4 Static Cmos RAM
 ICC2
VIH VOL VOH
VOR
Icccr
 Input Pulse Rise and Fall Times 20nsec
Timing Measurement Reference Level Volt
 ~I----- t CW2 ------ . t
 PIN Configuration Logic Symbol
Schottky Bipolar
 Conditions of Test
Voo- --- ---T
 Power Supply Current Drain and Power Dissipation
All driver outputs are in the state indicated
 Typical System
 Dynamic Memory Refresh Controller
Page
 8212 8255 8251
Page
 PIN Configuration Logic Diagram
EIGHT-BIT INPUT/OUTPUT Port
 Functional Description
OS2
 Basic Schematic Symbols
II. Gated Buffer 3·STATE
Are 3-state
Gated Buffer
 III. Bi-Directional Bus Driver
IV. Interrupting Input Port
Interrupt Instruction Port
BI-DIRECTIONAL BUS Driver
 VI. Output Port With Hand-Shaking
VII Status Latch
8080 4
OvJ \.. -4~
 Viii System
OUT
Vee
System
 IX System
 DalN-t?!NrJ
1G~D L-~
 Characteristics
Absolute Maximum Ratings·
 Typical Characteristics
052 ~
 OUT
Tpw
 Switching Characteristics
TA = OC to + 75C Vee = +5V ± 5%
12 pF
 Programmable Peripheral Interface
~~~lEI~S 1-- +SV
 General
Data Bus Buffer
Read/Write and Control Logic
Basic Functional Description
 Reset
PIN Configuration
Group a and Group B Controls
Ports A, B, and C
 Mode Selection
Single Bit Set/Reset Feature
Detailed Operational Description
PA 7 ·pAo
 Operating Modes Mode 0 Basic Input/Output
Mode 0 Timing
Interrupt Control Functions
 Mode 0 Port Definition Chart
Mode 0 Configurations
 119
 Operating Modes Mode 1 Strobed Input/Output
· / ,4
 Input Control Signal Definition
IBF Input Buffer Full F/F
Intr Interrupt Request
Inte a
 Output Control Signal Definition
Intea
 Combinations of Mode
Bi-Directional Bus I/O Control Signal Definition
Operating Modes
Output Operations
 Mode 2 Control Word
Mode 2 Bi-directional Timing
 Mode 2 Combinations
Mode 2 and Mode 0 Output
 Special Mode Combination Considerations
Mode Definition Summary Table
Source Current Capability on Port B and Port C
Reading Port C Status
 Applications
Printer Interface
Keyboard and Display Interface
Keyboard and Terminal Address Interface
 PCO
~.LEFT/RIGHT
 Silicon Gate MOS
 Characteristics TA = oc to 70C Vee = +5V ±5% vss = OV
Vil Input Low Voltage
Input High Voltage Val Output Low Voltage IOl = 1.6mA
Time From STB = 0 To IBF
 Mode 0 Basic Input
 Mode 1 Strobed Input
 Mode 2 Bi-directional
Page
 Programmable Communication Interface
 Reset Reset
General
ReadlWrite Control logic
ClK Clock
 Modem Control
DSR Data Set Ready
TxE Transmitter Empty
DTR Data Termin·al Ready
 Receiver Buffer
Receiver Control
RxRDY Receiver Ready
RxC Receiver Clock
 Mode Instruction
Command Instruction
Detailed Operation Description
Programming
 Mode Instruction Definition
Asynchronous Mode Transmission
Asynchronous Mode Receive
Data C~~RACTER
 Synchronous Mode Transmission
Synchronous Mode Receive
Mode Instruction Format, Synchronous Mode
Synchronous Mode, Transmission Format
 Command Instruction Definition
Command Instruction Format
Status Read Definition
Status Read Format
 Asynchronous Serial Interface to CRT Terminal, DC-9600 Baud
Asynchronous Interface to Telephone Lines
Synchronous Interface to Terminal or Peripheral Device
Synchronous Interface to Telephone Lines
 Capacitance
Icc
IOL
 TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol Parameter
Typ
 RxD
SRX ~4IlI
~AST BIT ,----1
RXD~
 Peripherals
Page
 High Speed 1 OUT of 8 Binary Decoder
 Enable Gate
Decoder
System
 Using a very similar circuit to the I/O port decoder, an ar
Port Decoder
Chip Select Decoder
24K Memory Interface
 Logic Element Example
\lJ
JJ,.--+-I----.....1
Ill
 Characteristics TA = OOC to +75C, Vee = 5.0V ±5%
Typical Characteristics
Symbol VOL VOH
8205
 Switching Characteristics Conditions of Test Test Load
Address or Enable to Output Delay VS. Load Capacitance
Address or Enable to Output Delay VS. Ambient Temperature
Test Waveforms
 PIN Configuration
~ R
~ ~
 Interrupts in Microcomputer Systems
Polled Method
Interrupt Method
 Priority Encoder
Current Status Register
 Control Signals
INTE, elK
ElR, ETlG, ENGl
AO, A1, A2
 Level Controller
Basic Operation
 I I
Level Controller
 Cascading
 Operating Characteristics
Symbol Parameter Limits Unit Conditions Min Typ.£1
Los
Absolute Maximum Ratings
 Characteristics and Waveforms TA = oc to +70C, vcc = +5V ±5%
 Schottky Bipolar
 +-......---- n cs
8216 8226
 Bi-Directional Driver
Control Gating OlEN, CS
 Applications of 8216/8226
Memory and 1/0 Interface to a Bi-directional Bus
Large microcomputer systems it is often necessary to pro
 IcC Power Supply Current 120
Input Load Current OlEN, CS VF =0.45
Input Load Current All Other Inputs VF =0.45
Input Leakage Current OlEN, CS VR =5.25V
 Waveforms
OUT
Page
 8253 8257 8259
Page
 Programmable Interval Timer
It uses nMOS technology ~Jmodesof operation are
 Block Diagram
Preliminary Functional Description
System Interface
System Interface
 Programmable DMA Controller
 System Interface
Dack 2
System Application
 CS-------It
 LJJ
 CPU Group
ROMs RAMs
Peripheral Coming Soon
Intel
 ~~~1
735~
It-j
 \.--.J.. ~~~l
·34o~
Lead Plastic Dual IN-LINE Package P
Lead CerDIP Dual IN-LINE Package D
 Sales and Marketing Offices
 Distributors
Page
Page
Page
Page
Page
Page
 Instruction SET
 Instruction SET
Summary of Processor Instructions By Alphabetical Order
 Microcomputer System Users Registration Card
 Intel Corporation
Microcomputer Systems Bowers Avenue Santa Clara, CA
 Inter