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Intel 8080 manual Summary of Processor Instructions, Llf17

Models: 8080

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SILICON GATE MOS M8080A

INSTRUCTION SET

Summary of Processor Instructions

Mnemonic				Instruction Code (1)						Clock (21
Mnemonic	Description	07	06	Os	04	03	02	0,	Do	Cycles
MOV r1 ,r2	Move register to register	0	1	0	0	0	S	S	S	5
MOV M,r	Move register to memory	0	1	1	1	0	S	S	S	7
MOVr,M	Move memory to register	0	1	0	0	0	1	1	0	7
HlT	Halt	0	1	1	1	0	1	1	0	7
MVIr	Move immediate register	0	0	0	0	0	1	1	0	7
MVIM	Move immediate memory	0	0	1	1	0	1	1	0	10
INR r	Increment register	0	0	0	0	0	1	0	0	5
OCR r	Decrement register	0	0	0	0	0	1	0	1	5
INR M	Increment memory	0	0	1	1	0	1	0	0	10
OCR M	Decrement memory	0	0	1	1	0	1	0	1	10
ADO r	Add register to A	1	0	0	0	0	S	S	S	4
ADC r	Add register to A with carry	1	0	0	0	1	S	S	S	4
SUB r	Subtract register from A	1	0	0	1	0	S	S	S	4
SBB r	Subtract register from A	1	0	0	1	1	S	S	S	4
	with borrow
ANA r	And register with A		0	1	0	0	S	S	S	4
XRA r	Exclusive Or register with A		0	1	0	1	S	S	S	4
ORA r	Or register with A		0	1	1	0	S	S	S	4
CMPr	Compare register with A		0	1	1	1	S	S	S	4
ADD M	Add memory to A		0	0	0	0	1	1	0	7
AOC M	Add memory to A with carry		0	0	0	1	1	1	0	7
SUB M	Subtract memory from A		0	0	1	0	1	1	0	7
SBB M	Subtract memory from A		0	0	1	1	1	1	0	7
	with borrow
ANAM	And memory with A		0	1	0				0
XRA M	Exclusive ar memory with A		0	1	0				0
ORA M	Or memory with A		0	1	1				0
CMPM	Compare memory with A		0	1	1				0
ADI	Add immediate to A		1	0	0				0
ACI	Add immediate to A with		1	0	0				0
	carry
SUI	Subtract immediate from A
SBI	Subtract immediate from A
	with borrow
ANI	And immediate with A				0				0
XRI	Exclusive Or immediate with				0				0
	A
ORI	Or immediate with A	1	1	1	1	0				7
CPI	Compare immediate with A	1	1	1	1	1				7
RLC	Rotate A left	0	0	0	0	0				4
RRC	Rotate A right	0	0	0	0	1				4
RAL	Rotate A left through carry	0	0	0	1	0				4
RAR	Rotate A right through	0	0	0	1	1				4
	carry
JMP	Jump unconditional			0	0	0	0	1	1	10
JC	Jump on carry			0	1	1	0	1	0	10
JNC	Jump on no carry			0	1	0	0	1	0	10
JZ	Jump on zero			0	0	1	0	1	0	10
JNZ	Jump on no zero			0	0	0	0	1	0	10
JP	Jump on positive			1	1	0	0	1	0	10
JM	Jump on minus			1	1	1	0	1	0	10
JPE	Jump on parity even			1	0	1	0	1	0	10
JPO	Jump on parity odd			1	0	0	0	1	0	10
CALL	Call unconditional			0	0	1	1	0	1	17
CC	Call on carry			0	1	1	1	0	0	11/17
CNC	Call on no carry			0	1	0	1	0	0	11/17
CZ	Call on zero			0	0	1	1	0	0	11/17
CNZ	Call on no zero			0	0	0	1	0	0	11/17
CP	Call on positive			1	1	0	1	0	0	11/17
CM	Call on minus			1	1	1	1	0	0	11/17
CPE	Call on parity even			1	0	1	1	0	0	llf17
CPO	Call on parity odd			1	0	0	1	0	0	l1f17
RET	Return			0	0	1	0	0	1	10
RC	Return on carry			0	1	1	0	0	0	5/11
RNC	Return on no carry			0	1	0	0	0	0	5/11

				Instruction Code [n						Clock (2)
Mnemonic	Description	07	06	Os	04	03	02	01	00	Cycles
RZ	Return on zero	1	1	0	0	1	0	0	0	5/11
RNZ	Return on no zero	1	1	0	0	0	0	C	0	5/11
RP	Return on positive	1	1	1	1	0	0	0	0	5/11
RM	Return on minus	1	1	1	1	1	0	0	0	5/11
RPE	Return on parity even	1	1	1	0	1	0	0	0	5/11
RPO	Return on parity odd	1	1	1	0	0	0	0	0	5/11
RST	Restart	1	1	A	A	A	1	1	1	11
IN	Input	1	1	0	1	1	0	1	1	10
OUT	Output	1	1	0	1	0	0	1	1	10
LXI B	Load Immediate register	0	0	0	0	0	0	0	1	10
	Pair B & C
LXI 0	Load immediate register						0			10
	Pair 0 & E
LXI H	Load immediate register									10
	Pair H & L
LXISP	Load immediate stack pointer					0		0		10
PUSH B	Push register Pair B & C on					0		0		11
	stack
PUSH 0	Push register Pair 0 & E on									11
	stack
PUSH H	Push register Pair H & L on									11
	stack
PUSH PSW	Push A and Flags					0		0		11
	on stack
POP B	Pop register pair B & C off					0				10
	stack
POP 0	Pop register pair 0 & E off									10
POP H	stack
POP H	Pop register pair H & L off									10
	stack
POP PSW	Pop A and Flags									10
	off stack
STA	Store A direct		0				0		0	13
LOA	Load A direct		0				0		0	13
XCHG	Exchange 0 & E, H& L		1				0		1	4
	Registers
XTHL	Exchange top of stack, H& L	1	1	1	0	0	0	1	1	18
SPHL	H& L to stack pointer	1	1	1	1	1	0	0	1	5
PCHL	H& L to program counter	1	1	1	0	1	0	0	1	5
DAD B	Add B & C to H & L	0	0	0	0	1	0	0	1	10
DAD 0	Add 0 & E to H & L	0	0	0	1	1	0	0	1	10
DAD H	Add H & L to H & L	0	0	1	0	1	0	0	1	10
DAD SP	Add stack pointer to H & l	0	0	1	1	1	0	0	1	10
STAX B	Store A indirect	0	0	0	0	0	0	1	0	7
STAX 0	Store A indirect	0	0	0	1	0	0	1	0	7
LOAX B	Load A indirect	0	0	0	0	1	0	1	0	7
LOAX 0	Load A indirect	0	0	0	1	1	0	1	0	7
INX B	Increment B & C registers	0	0	0	0	0	0	1	1	5
INX 0	Increment 0 & E registers	0	0	0	1	0	0	1	1	5
INX H	Increment H & L registers	0	0	1	0	0	0	1	1	5
INX SP	Increment stack pointer	0	0	1	1	0	0	1	1	5
OCX B	Decrement B & C	0	0	0	0	1	0	1	1	5
OCX 0	Decrement 0 & E	0	0	0	1	1	0	1	1	5
OCX H	Decrement H & L	0	0	1	0	1	0	1	1	5
OCX SP	Decrement stack pointer	0	0	1	1	1	0	1	1	5
CMA	Complement A	0	0	1	0	1	1	1	1	4
STC	Set carry	0	0	1	1	0	1	1	1	4
CMC	Complement carry	0	0	1	1	1	1	1	1	4
OAA	Decimal adjust A	0	0	1	0	0	1	1	1	4
SHLD	Store H & l direct	0	0	1	0	0	0	1	0	16
LHlO	Load H & L direct	0	0	1	0	1	0	1	0	16
EI	Enable Interrupts	1	1	1	1	1	0	1	1	4
01	Disable interrupt	1	1	1	1	0	0	1	1	4
NOP	No-operation	0	0	0	0	0	0	0	0	4

NOTES: 1. DOD or SSS - 000 B - 001 C - 010 0 - 011 E - 100 H - 101 L - 110 Memory - 111 A. 2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags.

Image 93

Intel 8080 manual Summary of Processor Instructions, Llf17

8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.

Contents

Page System Controller for 8080A Clock Generator for 8080AProgrammable Communication Interface Programmable Peripheral InterfaceContents 127 Peri pheralsChapter Packaging Information Page Advantages of Designing With Microcomputers Microcomputer Design AidsConventional System Programmed Logic Applications Example Iii1IIII~Iff1 Peripheral Devices Encountered ApplicationTypical Computer System Architecture of a CPUAccumulator Instruction Register and Decoder Program Counter Jumps, Subroutines and the StackAddress Registers Control CircuitryArithmetic/Logic Unit ALU Computer OperationsMemory Read Instruction FetchMemory Write Wait memory synchronizationPage Page 8080 Photomicrograph With Pin Designations INTE~Registers Architecture of the 8080 CPUInstruction Register and Control Arithmetic and Logic Unit ALUData Bus Buffer Processor CycleMachine Cycle Identification Halt State Transition SequenceStatus Word Chart Status Bit DefinitionsStatus Information Definition ?~~ CPU State Transition DiagramRr\ ONE ,----- ~ ~2. State Definitions State Associated ActivitiesInterrupt Sequences RLrL- rL rL rL-rL- rLrL¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL Hold Sequences Halt SequencesSTART-UP of the 8080 CPU 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~iA~~ll,12 ~iA~~~11~A~~~ll ~iA~~~11111 000 001 010 011 100 101 ValueBasic System Operation Typical Computer System Block Diagram8080 CPU CPU Module DesignClock Generator and High Level Driver Clock Generator DesignClK 0.......-..-.-----.. tf1A TTL ~50nsHigh Level Driver Design Ststb !1 Page Interfacing the 8080 CPU to Memory and I/O Devices ROM InterfaceRAM Interface Ill General Theory InterfaceIsolated I/O Memory Mapped I/OAddressing Interface ExampleMemr to 15 Format 13 Format8080 Instruction SET Instruction and Data FormatsByte Two Byte OneByte Three I D7 Addressing ModesSymbols Meaning Symbols and AbbreviationsDescription Format AllData Transfer Group Content of register r2 is moved to register r1MOV r1, r2 Move Register Reg. indirect0 I R 0 I R pArithmetic Group 0 I1 I 0 I 0 o0 I D I D R 0 ILogical Group I IOCR M Decrement memory Cycles States Addressing reg. indirect Flags Z,S,P ,CY,ACI 1 I 1 o I 1 I 1 I I 0 I 1 I 1 I~11~ 1 1 10 I 0 1 I 0 I 1 I0 I 0 I Cycles States Flags none000 Branch GroupI c c I c I 0 I 0 I Ccondition addrSP ~ SP + I 1 o Stack, I/O, and Machine Control GroupPush rp 1 I R~ SP + Exchange stack top with Hand L~ data Cycles States Flags NoneInstruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page PIN Names Schottky BipolarGeneral Functional DescriptionOscillator Clock GeneratorStstb Status Strobe Power-On Reset and Ready Flip-FlopsCrystal Requirements Characteristics8pF InputExample Characteristics For tCY = 488.28 nsT42 T01 T02 T03 Toss TORS tORH tOR FMAXDbin PIN Configuration Block DiagramBlock GeneralInta None Control SignalsTE~r Characteristics TA = Oc to 70C Vee = 5V ±5%Waveforms Hlda to Read Status OutputsStstb GoUTVTH VCC=5VGND ---. r ·-c?oo .H Intel Silicon Gate MOS 8080 aVee Vss8080A Functional PIN Definition Absolute Maximum RATINGS· CharacteristicsCapacitance IOl = 1.9mA on all outputs~I~~~ =..... -r-DATAINTiming Waveforms ~~1 t CYTypical ~ Output Delay VS. a Capacitance CharacteristicsTypical Instructions Instruction SETSummary of Processor Instructions Silicon Gate MOS 8080.AInfel Silicon Gate MOS 8080A-1 Symbol Parameter Typ MaxUnit Fft~l ~tOF.I~-t TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 Cout +10J1A VAOOR/OATA = VSS + O.45VUnit Test Condition Symbol Parameter MinMin. Max. Unit Test Condition Typical ~ Output Delay VS. ~ CapacitancePage Intel . Silicon Gate MOS M8080A Register to regist~r, memory refer Immediate mode or I/O instructionsEnce, arithmetic or logical, rotate Interrupt instructionsLlf17 Summary of Processor InstructionsM8080A Functional PIN Definition Silicon Gate MOS M8080AAbsolute Maximum Ratings IOL = 1.9mA on all outputsOperation Symbol Parameter Min. Max Unit Test Condition ~I~ Silicon Gate MOS M8080APage ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A Operating Characteristics PIN ConnectionsVoo 1N= Vee Switching Characteristics~10% = V ceCs=o.~ \ \Symbol Test Operating Characteristics for Programming OperationCharacteristics for Programming Operation SYMBOLTESTMIN. TYP. MAX. Unit ConditionsCS = OV Switching Characteristics for Programming OperationProgramming Operation of the 8702A Program OperationII. Programming of the 8702A Using Intel Microcomputers Operation of the 8702A in Program ModeIII a Erasing Procedure Programming Instructions for the 8702APage PIN Names PIN Configurations Block DiagramIII CommentIBB VOH1Test Conditions Symbol Parameter Typ. Max. Unit ConditionsWaveforms Max UnitParameter Min TpF Program Pulse Fall TimeProgramming Current RnA Program Pulse Amplitude Read/Program/Read Transitions CS/WE = +12V+-------1 PEEEf!1EJEZPlEzz$m=2!·m·· Icc 150 rSilicon Gate MOS MAX Unit CommentCS=O.O Outa~~~H --4!~--~N-~-TA-AL-~-DU-T--~\ 100 ns 7001 JJ.s200ns 500ns 300 ns Cs .. o.~ ~r Typical CharacteristicsSilicon Gate MOS Ilpc IlclIlkc ILOConditions of Test for Characteristics CoUTCIN ~ ~ ~ Marking Mask Option SpecificationsPppp Customer Number OateTitle Card ~ r ------ + -- t --- . L . ------ rJBlank 79-80Intel Silicon Gate MOS ROM 8316A PIN Configuration Block Diagram400 Conditions of Test forCAPACITANCE2 TA = 25C, f = 1 MHz Waveforms OU~TVALIDILICO.N Gate MOS ROM 8316A Typical D.C. CharacteristicsNumber Oate CustomerSTO Mask Option Speci FicationsCOM~ANY Name Title CardRAMs Page Silicon Gate MOS PIN Configuration Logic Symbol Block Diagram= OC ~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~=10H = -150 p.A +----+00 ~ Conditions of TestPage Silicon Gate MOS PIN Configuration Logic Symbol Block DiagramIII Symbol Parameter Min. Typ.rICC1 ICC2550 200 Write 1~-tAW--.I-----IInput Pulse Rise and Fall Times 20nsec Timing Measurement Reference Level VoltPage Silicon Gate MOS 5V to +7V Power Dissipation WattComment TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified+--~~~TL~~~EEt~~~P-.± 85o-·-···TCapacitance T a = 25C, f = 1MHz Conditions of Test~~~b~.J Typical A.C. CharacteristicsSilicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 450 230300 Access Time VS Ambient Temperature VIN Limits VS. TemperatureAccess Time VS LOAD·CAPACITANCE Output Source Current VSPIN Configuration Logic Symbol Block Diagram Fully Decoded Random Access BIT Dynamic MemoryIOOAV2 Silicon Gate MOS 81078·4IMP~ri~~CE II.~4000 Read CycleRef = Write CycleTypical Characteristics Symbol Parameter Min Max RWc 590 CDNumbers in parentheses are for minimum cycle timing in ns Standby Power Power DissipationRefresh System Interfaces and FilteringTypical System BIT 256 x 4 Static Cmos RAM VIH VOL VOH ICC2VOR IcccrTiming Measurement Reference Level Volt Input Pulse Rise and Fall Times 20nsec~I----- t CW2 ------ . t Schottky Bipolar PIN Configuration Logic SymbolVoo- --- ---T Conditions of TestAll driver outputs are in the state indicated Power Supply Current Drain and Power DissipationTypical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page EIGHT-BIT INPUT/OUTPUT Port PIN Configuration Logic DiagramOS2 Functional DescriptionII. Gated Buffer 3·STATE Basic Schematic SymbolsAre 3-state Gated BufferIV. Interrupting Input Port III. Bi-Directional Bus DriverInterrupt Instruction Port BI-DIRECTIONAL BUS DriverVII Status Latch VI. Output Port With Hand-Shaking8080 4 OvJ \.. -4~OUT Viii SystemVee SystemIX System 1G~D L-~ DalN-t?!NrJAbsolute Maximum Ratings· Characteristics052 ~ Typical CharacteristicsTpw OUTSwitching Characteristics TA = OC to + 75C Vee = +5V ± 5%12 pF ~~~lEI~S 1-- +SV Programmable Peripheral InterfaceData Bus Buffer GeneralRead/Write and Control Logic Basic Functional DescriptionPIN Configuration ResetGroup a and Group B Controls Ports A, B, and CSingle Bit Set/Reset Feature Mode SelectionDetailed Operational Description PA 7 ·pAoOperating Modes Mode 0 Basic Input/Output Mode 0 TimingInterrupt Control Functions Mode 0 Configurations Mode 0 Port Definition Chart119 · / ,4 Operating Modes Mode 1 Strobed Input/OutputIBF Input Buffer Full F/F Input Control Signal DefinitionIntr Interrupt Request Inte aIntea Output Control Signal DefinitionBi-Directional Bus I/O Control Signal Definition Combinations of ModeOperating Modes Output OperationsMode 2 Bi-directional Timing Mode 2 Control WordMode 2 and Mode 0 Output Mode 2 CombinationsMode Definition Summary Table Special Mode Combination ConsiderationsSource Current Capability on Port B and Port C Reading Port C StatusPrinter Interface ApplicationsKeyboard and Display Interface Keyboard and Terminal Address Interface~.LEFT/RIGHT PCOSilicon Gate MOS Vil Input Low Voltage Characteristics TA = oc to 70C Vee = +5V ±5% vss = OVInput High Voltage Val Output Low Voltage IOl = 1.6mA Time From STB = 0 To IBFMode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface General Reset ResetReadlWrite Control logic ClK ClockDSR Data Set Ready Modem ControlTxE Transmitter Empty DTR Data Termin·al ReadyReceiver Control Receiver BufferRxRDY Receiver Ready RxC Receiver ClockCommand Instruction Mode InstructionDetailed Operation Description ProgrammingAsynchronous Mode Transmission Mode Instruction DefinitionAsynchronous Mode Receive Data C~~RACTERSynchronous Mode Receive Synchronous Mode TransmissionMode Instruction Format, Synchronous Mode Synchronous Mode, Transmission FormatCommand Instruction Format Command Instruction DefinitionStatus Read Definition Status Read FormatAsynchronous Interface to Telephone Lines Asynchronous Serial Interface to CRT Terminal, DC-9600 BaudSynchronous Interface to Terminal or Peripheral Device Synchronous Interface to Telephone LinesCapacitance IccIOL Typ TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol ParameterSRX ~4IlI RxD~AST BIT ,----1 RXD~Peripherals Page High Speed 1 OUT of 8 Binary Decoder Enable Gate DecoderSystem Port Decoder Using a very similar circuit to the I/O port decoder, an arChip Select Decoder 24K Memory Interface\lJ Logic Element ExampleJJ,.--+-I----.....1 IllTypical Characteristics Characteristics TA = OOC to +75C, Vee = 5.0V ±5%Symbol VOL VOH 8205Address or Enable to Output Delay VS. Load Capacitance Switching Characteristics Conditions of Test Test LoadAddress or Enable to Output Delay VS. Ambient Temperature Test WaveformsPIN Configuration ~ R~ ~ Interrupts in Microcomputer Systems Polled MethodInterrupt Method Current Status Register Priority EncoderINTE, elK Control SignalsElR, ETlG, ENGl AO, A1, A2Basic Operation Level ControllerLevel Controller I ICascading Symbol Parameter Limits Unit Conditions Min Typ.£1 Operating CharacteristicsLos Absolute Maximum RatingsCharacteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar 8216 8226 +-......---- n csControl Gating OlEN, CS Bi-Directional DriverApplications of 8216/8226 Memory and 1/0 Interface to a Bi-directional BusLarge microcomputer systems it is often necessary to pro Input Load Current OlEN, CS VF =0.45 IcC Power Supply Current 120Input Load Current All Other Inputs VF =0.45 Input Leakage Current OlEN, CS VR =5.25VOUT WaveformsPage 8253 8257 8259 Page It uses nMOS technology ~Jmodesof operation are Programmable Interval TimerPreliminary Functional Description Block DiagramSystem Interface System InterfaceProgrammable DMA Controller System Interface Dack 2System Application CS-------It LJJ ROMs RAMs CPU GroupPeripheral Coming Soon Intel~~~1 735~It-j ·34o~ \.--.J.. ~~~lLead Plastic Dual IN-LINE Package P Lead CerDIP Dual IN-LINE Package DSales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Summary of Processor Instructions By Alphabetical Order Instruction SETMicrocomputer System Users Registration Card Microcomputer Systems Bowers Avenue Santa Clara, CA Intel CorporationInter