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Intel 8080 manual R 0 I, I D I D

Models: 8080

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SUB M (Subtract memory)

(A) ~ (A) - ((H) (L))

The content of the memory location whose address is contained in the Hand L registers is subtracted from the content of the accumulator. The result is placed in the accumulator.

		o	o
	Cycles:	2
	States:	7
	Addressi ng:	reg. indirect
	Flags:	Z,S,P,CY,AC
SUI data	(Subtract immediate)
(A) ~ (A) - (byte 2)

The content of the second byte of the instruction is subtracted from the content of the accumulator. The result is placed in the accumulator.

o

data

Cycles: 2

States: 7

Addressing: immediate

Flags: Z,S,P,CY,AC

SBB r (Subtract Register with borrow)

(A) ~ (A) - (r) - (CY)

The content of register r and the content of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator.

1 I 0 I 0	S I S I S I
Cycles:	1
States:	4
Addressing:	register
Flags:	Z,S,P ,CY ,AC

SBa M (Subtract memory with borrow)

(A) ~ (A) - ((H) (L)) - (CY)

The content of the memory location whose address is

contained in the Hand L registers and the content of

the CY flag are both subtracted from the accumula-
tor. The result is placed in the accumulator.
1 I 0	,	1 I	1 I 1 I 0 I
1 I 0	0	1 I	1 I 1 I 0 I
		Cycles:	2
		States:	7
	Addressing:		reg. indirect
		Flags:	Z,S,P,CY,AC

SBI data (Subtract immediate with borrow)

(A) ~ (A) - (byte 2) - (CY)

The contents of the second byte of the instruction and the contents of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator.

1 I	I 0	o
	data
	Cycles:	2
	States:	7
	Addressing:	immediate
	Flags:	Z,S,P,CY,AC

INR r (Increment Register)

(r) ~ (r) + 1

The content of register r is incremented by one. Note: All condition flags except CY are affected.

D 1 r 0 I 0

Cycles: 1

States: 5

Addressi ng: register

Flags: Z,S,P,AC

INR M (Increment memory) ((H) (L)) ~ ((H) (L)) + 1

The content of the memory location whose address is contained in the Hand L registers is incremented by one. Note: All condition flags except CY are affected.

o I 0

o

o

o

Cycles: 3

States: 10

Addressing: reg. indirect

Flags: Z,S,P,AC

OCR r(Decrement Register)

(r) ~ (r)-1

The content of register r is decremented by one. Note: All condition flag~ except CY are affected.

0 I 0 I D I D	D I 1 I 0	I 1
Cycles:	1	.f'
States:	5
Addressing:	register
Flags:	Z,S,P,AC

4-7

Image 51

Intel 8080 manual R 0 I, I D I D

Contents

Page Programmable Peripheral Interface Clock Generator for 8080ASystem Controller for 8080A Programmable Communication InterfaceContents 127 Peri pheralsChapter Packaging Information Page Advantages of Designing With Microcomputers Microcomputer Design AidsConventional System Programmed Logic Applications Example Iii1IIII~Iff1 Peripheral Devices Encountered ApplicationTypical Computer System Architecture of a CPUAccumulator Instruction Register and Decoder Program Counter Jumps, Subroutines and the StackComputer Operations Control CircuitryAddress Registers Arithmetic/Logic Unit ALUWait memory synchronization Instruction FetchMemory Read Memory WritePage Page 8080 Photomicrograph With Pin Designations INTE~Registers Architecture of the 8080 CPUProcessor Cycle Arithmetic and Logic Unit ALUInstruction Register and Control Data Bus BufferMachine Cycle Identification Halt State Transition SequenceStatus Word Chart Status Bit DefinitionsStatus Information Definition ?~~ CPU State Transition DiagramRr\ ONE ,----- ~ ~2. State Definitions State Associated ActivitiesInterrupt Sequences RLrL- rL rL rL-rL- rLrL¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL Hold Sequences Halt SequencesSTART-UP of the 8080 CPU 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~iA~~~11 ~iA~~~11~iA~~ll,12 ~A~~~ll111 000 001 010 011 100 101 ValueBasic System Operation Typical Computer System Block DiagramClock Generator Design CPU Module Design8080 CPU Clock Generator and High Level DriverClK 0.......-..-.-----.. tf1A TTL ~50nsHigh Level Driver Design Ststb !1 Page Interfacing the 8080 CPU to Memory and I/O Devices ROM InterfaceRAM Interface Ill Memory Mapped I/O InterfaceGeneral Theory Isolated I/OAddressing Interface ExampleMemr to 15 Format 13 Format8080 Instruction SET Instruction and Data FormatsAddressing Modes Byte OneByte Two Byte Three I D7All Symbols and AbbreviationsSymbols Meaning Description FormatReg. indirect Content of register r2 is moved to register r1Data Transfer Group MOV r1, r2 Move Register0 I R 0 I R p0 I 0 o 0 IArithmetic Group 1 I0 I D I D R 0 ICycles States Addressing reg. indirect Flags Z,S,P ,CY,AC I ILogical Group OCR M Decrement memory1 1 1 I 0 I 1 I 1 II 1 I 1 o I 1 I 1 I ~11~Cycles States Flags none 0 I 1 I0 I 0 1 I 0 I 0 I000 Branch GroupI c c I c I 0 I 0 I Ccondition addrSP ~ SP + 1 I R Stack, I/O, and Machine Control GroupI 1 o Push rpCycles States Flags None Exchange stack top with Hand L~ SP + ~ dataInstruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page PIN Names Schottky BipolarClock Generator Functional DescriptionGeneral OscillatorStstb Status Strobe Power-On Reset and Ready Flip-FlopsCrystal Requirements Characteristics8pF InputTORS tORH tOR FMAX Characteristics For tCY = 488.28 nsExample T42 T01 T02 T03 TossDbin PIN Configuration Block DiagramBlock GeneralInta None Control SignalsHlda to Read Status Outputs Characteristics TA = Oc to 70C Vee = 5V ±5%TE~r WaveformsVCC=5V GoUTStstb VTHGND ---. r ·-c?oo .H Intel Silicon Gate MOS 8080 aVee Vss8080A Functional PIN Definition IOl = 1.9mA on all outputs CharacteristicsAbsolute Maximum RATINGS· Capacitance~~1 t CY =..... -r-DATAIN~I~~~ Timing WaveformsTypical ~ Output Delay VS. a Capacitance CharacteristicsTypical Instructions Instruction SETSummary of Processor Instructions Silicon Gate MOS 8080.AInfel Silicon Gate MOS 8080A-1 Symbol Parameter Typ MaxUnit Fft~l ~tOF.I~-t TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 VAOOR/OATA = VSS + O.45V +10Cout J1AUnit Test Condition Symbol Parameter MinMin. Max. Unit Test Condition Typical ~ Output Delay VS. ~ CapacitancePage Intel . Silicon Gate MOS M8080A Interrupt instructions Immediate mode or I/O instructionsRegister to regist~r, memory refer Ence, arithmetic or logical, rotateLlf17 Summary of Processor InstructionsM8080A Functional PIN Definition Silicon Gate MOS M8080AAbsolute Maximum Ratings IOL = 1.9mA on all outputsOperation Symbol Parameter Min. Max Unit Test Condition ~I~ Silicon Gate MOS M8080APage ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A Operating Characteristics PIN ConnectionsVoo = V ce Switching Characteristics1N= Vee ~10%Cs=o.~ \ \SYMBOLTESTMIN. TYP. MAX. Unit Conditions Operating Characteristics for Programming OperationSymbol Test Characteristics for Programming OperationProgram Operation Switching Characteristics for Programming OperationCS = OV Programming Operation of the 8702AProgramming Instructions for the 8702A Operation of the 8702A in Program ModeII. Programming of the 8702A Using Intel Microcomputers III a Erasing ProcedurePage PIN Names PIN Configurations Block DiagramVOH1 CommentIII IBBMax Unit Symbol Parameter Typ. Max. Unit ConditionsTest Conditions WaveformsParameter Min TpF Program Pulse Fall TimeProgramming Current RnA Program Pulse Amplitude Read/Program/Read Transitions CS/WE = +12V+-------1 PEEEf!1EJEZPlEzz$m=2!·m·· Icc 150 rSilicon Gate MOS Outa CommentMAX Unit CS=O.O~~~H --4!~--~N-~-TA-AL-~-DU-T--~\ 100 ns 7001 JJ.s200ns 500ns 300 ns Cs .. o.~ ~r Typical CharacteristicsSilicon Gate MOS ILO IlclIlpc IlkcConditions of Test for Characteristics CoUTCIN ~ ~ ~ Customer Number Oate Mask Option SpecificationsMarking Pppp79-80 ~ r ------ + -- t --- . L . ------ rJTitle Card BlankIntel Silicon Gate MOS ROM 8316A PIN Configuration Block Diagram400 Conditions of Test forCAPACITANCE2 TA = 25C, f = 1 MHz Waveforms OU~TVALIDILICO.N Gate MOS ROM 8316A Typical D.C. CharacteristicsMask Option Speci Fications CustomerNumber Oate STOCOM~ANY Name Title CardRAMs Page Silicon Gate MOS PIN Configuration Logic Symbol Block Diagram+----+ ~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~== OC 10H = -150 p.A00 ~ Conditions of TestPage Silicon Gate MOS PIN Configuration Logic Symbol Block DiagramICC2 Symbol Parameter Min. Typ.rIII ICC1Timing Measurement Reference Level Volt Write 1~-tAW--.I-----I550 200 Input Pulse Rise and Fall Times 20nsecPage Silicon Gate MOS TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified Power Dissipation Watt5V to +7V CommentConditions of Test 85o-·-···T+--~~~TL~~~EEt~~~P-.± Capacitance T a = 25C, f = 1MHz~~~b~.J Typical A.C. CharacteristicsSilicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 450 230300 Output Source Current VS VIN Limits VS. TemperatureAccess Time VS Ambient Temperature Access Time VS LOAD·CAPACITANCEPIN Configuration Logic Symbol Block Diagram Fully Decoded Random Access BIT Dynamic MemoryIOOAV2 Silicon Gate MOS 81078·4IMP~ri~~CE II.~Write Cycle Read Cycle4000 Ref =Typical Characteristics Symbol Parameter Min Max RWc 590 CDNumbers in parentheses are for minimum cycle timing in ns System Interfaces and Filtering Power DissipationStandby Power RefreshTypical System BIT 256 x 4 Static Cmos RAM Icccr ICC2VIH VOL VOH VORTiming Measurement Reference Level Volt Input Pulse Rise and Fall Times 20nsec~I----- t CW2 ------ . t Schottky Bipolar PIN Configuration Logic SymbolVoo- --- ---T Conditions of TestAll driver outputs are in the state indicated Power Supply Current Drain and Power DissipationTypical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page EIGHT-BIT INPUT/OUTPUT Port PIN Configuration Logic DiagramOS2 Functional DescriptionGated Buffer Basic Schematic SymbolsII. Gated Buffer 3·STATE Are 3-stateBI-DIRECTIONAL BUS Driver III. Bi-Directional Bus DriverIV. Interrupting Input Port Interrupt Instruction PortOvJ \.. -4~ VI. Output Port With Hand-ShakingVII Status Latch 8080 4System Viii SystemOUT VeeIX System 1G~D L-~ DalN-t?!NrJAbsolute Maximum Ratings· Characteristics052 ~ Typical CharacteristicsTpw OUTSwitching Characteristics TA = OC to + 75C Vee = +5V ± 5%12 pF ~~~lEI~S 1-- +SV Programmable Peripheral InterfaceBasic Functional Description GeneralData Bus Buffer Read/Write and Control LogicPorts A, B, and C ResetPIN Configuration Group a and Group B ControlsPA 7 ·pAo Mode SelectionSingle Bit Set/Reset Feature Detailed Operational DescriptionOperating Modes Mode 0 Basic Input/Output Mode 0 TimingInterrupt Control Functions Mode 0 Configurations Mode 0 Port Definition Chart119 · / ,4 Operating Modes Mode 1 Strobed Input/OutputInte a Input Control Signal DefinitionIBF Input Buffer Full F/F Intr Interrupt RequestIntea Output Control Signal DefinitionOutput Operations Combinations of ModeBi-Directional Bus I/O Control Signal Definition Operating ModesMode 2 Bi-directional Timing Mode 2 Control WordMode 2 and Mode 0 Output Mode 2 CombinationsReading Port C Status Special Mode Combination ConsiderationsMode Definition Summary Table Source Current Capability on Port B and Port CKeyboard and Terminal Address Interface ApplicationsPrinter Interface Keyboard and Display Interface~.LEFT/RIGHT PCOSilicon Gate MOS Time From STB = 0 To IBF Characteristics TA = oc to 70C Vee = +5V ±5% vss = OVVil Input Low Voltage Input High Voltage Val Output Low Voltage IOl = 1.6mAMode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface ClK Clock Reset ResetGeneral ReadlWrite Control logicDTR Data Termin·al Ready Modem ControlDSR Data Set Ready TxE Transmitter EmptyRxC Receiver Clock Receiver BufferReceiver Control RxRDY Receiver ReadyProgramming Mode InstructionCommand Instruction Detailed Operation DescriptionData C~~RACTER Mode Instruction DefinitionAsynchronous Mode Transmission Asynchronous Mode ReceiveSynchronous Mode, Transmission Format Synchronous Mode TransmissionSynchronous Mode Receive Mode Instruction Format, Synchronous ModeStatus Read Format Command Instruction DefinitionCommand Instruction Format Status Read DefinitionSynchronous Interface to Telephone Lines Asynchronous Serial Interface to CRT Terminal, DC-9600 BaudAsynchronous Interface to Telephone Lines Synchronous Interface to Terminal or Peripheral DeviceCapacitance IccIOL Typ TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol ParameterRXD~ RxDSRX ~4IlI ~AST BIT ,----1Peripherals Page High Speed 1 OUT of 8 Binary Decoder Enable Gate DecoderSystem 24K Memory Interface Using a very similar circuit to the I/O port decoder, an arPort Decoder Chip Select DecoderIll Logic Element Example\lJ JJ,.--+-I----.....18205 Characteristics TA = OOC to +75C, Vee = 5.0V ±5%Typical Characteristics Symbol VOL VOHTest Waveforms Switching Characteristics Conditions of Test Test LoadAddress or Enable to Output Delay VS. Load Capacitance Address or Enable to Output Delay VS. Ambient TemperaturePIN Configuration ~ R~ ~ Interrupts in Microcomputer Systems Polled MethodInterrupt Method Current Status Register Priority EncoderAO, A1, A2 Control SignalsINTE, elK ElR, ETlG, ENGlBasic Operation Level ControllerLevel Controller I ICascading Absolute Maximum Ratings Operating CharacteristicsSymbol Parameter Limits Unit Conditions Min Typ.£1 LosCharacteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar 8216 8226 +-......---- n csControl Gating OlEN, CS Bi-Directional DriverApplications of 8216/8226 Memory and 1/0 Interface to a Bi-directional BusLarge microcomputer systems it is often necessary to pro Input Leakage Current OlEN, CS VR =5.25V IcC Power Supply Current 120Input Load Current OlEN, CS VF =0.45 Input Load Current All Other Inputs VF =0.45OUT WaveformsPage 8253 8257 8259 Page It uses nMOS technology ~Jmodesof operation are Programmable Interval TimerSystem Interface Block DiagramPreliminary Functional Description System InterfaceProgrammable DMA Controller System Interface Dack 2System Application CS-------It LJJ Intel CPU GroupROMs RAMs Peripheral Coming Soon~~~1 735~It-j Lead CerDIP Dual IN-LINE Package D \.--.J.. ~~~l·34o~ Lead Plastic Dual IN-LINE Package PSales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Summary of Processor Instructions By Alphabetical Order Instruction SETMicrocomputer System Users Registration Card Microcomputer Systems Bowers Avenue Santa Clara, CA Intel CorporationInter