Intel 8080 manual TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol Parameter, Typ

SILICON GATE MOS 8251

A.C. Characteristics:

TA = o°c to 70°C; VCC = 5.0V ±5%; Vss = OV
Symbol	Parameter	Min.	Typ.
tCY	Clock Period	.420
t</JW	Clock Pulse Width	220
tR,tF	Clock Rise and Fall Time	0
tWR	WRITE Pulse Width	430
tos	Data Set-Up Time for WR ITE	0
tOH	Data Hold Time for WR ITE	65
tAW	Address Stable before WR ITE	20
tWA	Address Hold Time for WR ITE	35
tRO	READ Pulse Width	430
too	Data Delay from READ	350
tOF	READ to Data Floating	150
tAR1	Address Stable before READ, CE (C/D)	50
tRA1	Address Hold Time for READ, CE	5
tRA2	Address Hold Time for READ, C/O	370
tOTx	TxD Delay from Falling Edge of TxC	1
tSRx	Rx Data Set-Up Time to Sampling Pulse	2
tHRx	Rx Data Hold Time to Sampling Pulse	2
fTx	Transmitter Input Clock Frequency
	1X Baud Rate	DC
	16X and 64X Baud Rate	DC
fRx	Receiver Input Clock Frequency
	1X Baud Rate	DC
	16X and 64X Baud Rate	DC
tTx	TxRDY Delay from Center of Data Bit
tRx	RxRDY Delay from Center of Data Bit	15
tiS	Internal Syndet Delay from Center of Data Bit	20
tES	External Syndet Set-Up Time before Falling
	Edge of RxC

Note: The TxC and Rxe frequencies have the following I imitation with respect to ClK. For ASYNC Mode, tTx or tRx ~ 4.5 tCY

For SYNC Mode, tTx or tRx ~ 30 tCY

Max. Unit Test Conditions

1.35JlS

300ns

50 ns ns ns ns ns ns ns

ns CL=100pF

ns Cl=100pF ns

ns ns

JlS CL=100pF

J.l.S Cl=100pF

J.l.S CL=100pF

56KHz

615 KHz

56KHz

615 KHz

16ClK Period CL=50pF

20ClK Period

25ClK Period

15ClK Period

5-145