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| Code(hex) |
| Name |
| Description |
96 |
| Boot Attempt |
| Set low stack Boot via INT 19h. | |
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| C0 |
| Base CPU test |
| Read/Write CPU registers |
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| C1 |
| Memory Presence |
| Base memory detect |
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| C2 | Early Memory |
| Board Initialization | |
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| C3 |
| Extend Memory |
| Turn on extended memory, cache initialization |
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| C4 | Special Display | First display initialization | ||
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| C5 | Early Shadow |
| Early shadow enable for fast boot | |
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| C6 |
| Cache presence |
| External cache s |
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| FF |
| Boot |
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| NVIDIA Added Post Codes |
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| Code(hex) |
| Name |
| Description |
| F0 |
| HW Ident | Identify HW in the system | |
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| F1 |
| SLAM Table |
| Register the slam tables |
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| F2 |
| Early SLAM table |
| Early SLAM table |
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| F3 |
| Init Com Port |
| COM port initialization |
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00 | HW Init |
| Initialize hardware devices | ||
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01 | Override Parameters |
| Override input parameters etc. before QUERY | ||
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04 | Process SPD |
| Read SPD & fill in arrays | ||
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08 | Query HW | Query the hardware devices | |||
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| 0C |
| Load ROM Table |
| ROM table pointer |
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10 | Init Memory |
| Initialize the Memory Controller | ||
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| Controller |
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11 | Init Memory |
| PLL Init | ||
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| Controller |
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12 | Init Memory |
| Query after Memory PLL has been set | ||
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| Controller |
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13 | Init Memory |
| Set Dynamic SPD values | ||
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| Controller |
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14 | Init Memory |
| Load Memory Info Structure | ||
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| Controller |
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15 | Init Memory |
| Load DIMM geometry (using SPD) | ||
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| Controller |
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16 | Init Memory |
| Prepare MRS variables | ||
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| Controller |
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17 | Init Memory |
| Probe memory geometry | ||
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| Controller |
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18 | Init Memory |
| Load PROD and PROD_C tables | ||
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| 117 |