
Installing and Configuring the EVGA nForce 680i SLI Motherboard
RAS to RAS Delay
The
Refresh Rate
This value is filled in by the system and can not be changed by the user.
Memory bank switch
The row Precharge time (tRP) is the minimum time between active commands and the read/writes of the next bank on the memory module. Adjustable from 1 to 15.
R to W Turnaround
The
R to R Timing
the
Row Cycle Time
The Row Cycle Time is the minimum time in cycles it take a row to complete a full cycle. This can be determined by tRC=tRAS+tRP. If this value is set too short, it can cause corruption of data. If this value is set too high, it causes a loss in performance but an increase in stability. Adjustable from 1 to 63 cycles
W to R Command Delay
The
W to W Timing
The
CAS Latency
The CAS Latency (tCL) is the time (in number of clock cycles) that elapses after the memory controller sends a request to read a memory location and before the data is sent to the module's output pins. The value shown cannot be changed.
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