Intel mcs-48 manual 10 CPU, Reset, Jump Test Condition Instructions Accumulator, Test Input-T1

Models: mcs-48

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SINGLE COMPONENT SYSTEM

PROG

 

~

 

)Cf)C

DATA IN

V ADDRESSJ FLOAT

 

------

14 BITS)

 

(4 BITS)

DATA OUT

~ DATA

 

(P20·P23)

~ OUT

 

----- ....

(4 BITS)

'---~(4~BIT=S)~---------------

BITS 0,1

 

BITS 2,3

 

 

01OO} PORT

OO}READ

 

 

01

WRITE

 

 

10 ADDRESS

10

OR

 

 

11

11

AND

PORT 2 FOR EXPANDED 1/0 WITH 8243

FIGURE 6. EXPANDED I/O TIMING DIAGRAM

2.10 CPU

The 8021 CPU has arithmetic and logical capability. A wide variety of arithmetic and logic instructions may be exercised, which affect the contents of the accumulator, and/or direct or indirect scratch pad loca- tions. Provisions have been made for simplified BCD arithmetic capability using the DAA, SWAP A, and XCHD instructions. In addition, MOVP A,@A allows table lookup for display formating and constants. The conditional branch logic within the processor enables several conditions inter- nal and external to the processor to be tested by the users program. Use the

conditional jump instructions with the tests listed below to effect a change in the program execution sequence.

 

Jump

Jump

Test

Condition

Instructions

Accumulator

A=O A"'O

JZ JNZ

Carry Flag

o 1

,JC

Timer Overflow Flag

1

JTF

Test Input-T1

o 1

JNT1, JT1

2.11 Reset

Apositive-going signal to the RESET input resets the necessary miscellaneous flip- flops and sets "the program counter and stack pOinter to zero.

2-24

Page 51
Image 51
Intel mcs-48 10 CPU, Reset, Jump Test Condition Instructions Accumulator, Carry Flag Timer Overflow Flag, Test Input-T1