Inter | Intel mcs-48 guide

inter

NEW HIGH PERF·ORMANCE

. 8049/8039/8039·6

SINGLE COMPONENT 8·BIT MICROCOMPUTER

*8049 Mask Programmable ROM

*8039 External ROM or EPROM *New 11 MHz Operation

•8·BitCPU, ROM, RAM, 1/0 In Single Package

•Single 5V:t 10% Supply

•1.36 ILsac Cycle; AU Instructions

1 or 2 Cycles

•Over 90 Instructions: 70% Single Byte

•Pin Compatible with 8048/8748

•2Kx 8 ROM

128 x 8 RAM

27110 Lines

•Interval TlmerlEvent Counter

•Easily Expandable Memory and 1/0

•Compatible with MCS Memory and 1/0

•Single Level Interrupt

The Intel~ 8049/8039/8039-6 Is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel'sN-channel silicon gate MOS process.

The 8049 contains a 2K x 8 program memory, a 128 x 8 RAM data memory, 27 I/O lines, and an 8·blttimer/counter in addition to on board oscillator and clock circuits. For systems that require extra C;llpabillty, the 8049 can be expanded using standard memories and MCS-80™/MCS·85TM peripherals. The 8039 is the equivalent toan 8049 without program

memory. The 8039·6is a lower speed (6 MHz) version of the 8039..

To reduce development problems to a minimum and provide maximum flexibility, two Interchangeable pin-compatible versions of this single component microcomputer exist: the B049 with factory-programmed mask ROM program memory for low-cost high volume production, and the 8039 without program memory for use with external program memories in prototype and preproduction systems.

This microprocessor is designed to be an efficient contl'olleras well as an arithmetic processor. The 8049 has exten- sive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results from an instruction set consisting mostly of single byte instructions and·no instructions over two bytes In length.

PIN CONFIGURATION

LOGIC SYMBOL

BLOCK DIAGRAM

8049

INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PROOUCl NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED. 'INTELCORPORATION. 1979

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Intel mcs-48 manual Inter

Contents

Page September MCS-48 Family of Single Chip Microcomputers Usersmanual Prompt BXPMultibus Credit Table of Contents 8051/8751/8031 Microcomputer Chapters Packing Information Emulation BoardEmulation Board 10-19 UPP-103 Universal Prom Programmer Insite UsersLibraryPage Ntroduction Page Introduction to MCS-48 8021 is code compatible but not pin compatible with Introduction5.0 and 10.0 J,Lsec Cycle Versions Eprom IntroductionTil Introduction Accumulator Function of a ComputerTypical Computer System Architecture of a CPU Program Counter Jumps, Subroutines and the Stack Arithmetic/Logic Unit ALU Three levels of subroutines may be ac- commodatedInstruction Register and Decoder Address Registers Instruction Fetch Control CircuitryComputer Operations Timing Interrupts Memory WriteInput/Output To the next instructions When finished the processor continues on MOV R2, #05 Step No. Hex Code Assembly Code MOV RO, #32Our machine language program then becomes Step Hex Code SUB R7 ADD A, # ALFA*BETA/2Cpla ADD A, REG Function Definition Hardware ConfigurationDeveloping An MCS-48 Based Product Education Prompt Production Intellec Development SystemPage Single Component MCS-4S S~stem Page Arithmetic Section SummaryArchitecture ~BUS Location Single Component System Input/Output Single Component System Single Component System Pointer R23 +--1 R Jump Conditions Interrupt Timing Oscillator As a TimerAs an Event Counter Clock and Timing Circuits ALE --f---+--+ Instruction 111 LOVI RUN Stop Power Down ModeBUS PCO·7 Pin Description Number Function 00-07Designation Prog Programming, Verifying and Erasing Eprom Reset Single Component System Disabling Internal Program Memory ResetTest and Debug Single Step Reading Internal Program Memory Following is a functional description of the major elements Program Memory Oscillator and Clock Timer/Event Counter QUASI-BIDIRECTIONAL Port Structure Input/Output Capabilities Expanded I/O 1 T1 InputHigh Current Outputs Jump Test Condition Instructions Accumulator ResetCarry Flag Timer Overflow Flag 10 CPU Data Memory Functional SpecificationsProgram Memory See the 8021 description, .8, for a com- plete explanation 15Timer/Event CounterOscillator and Clock Port 0 Comparator Inputs Test and Interrupt Inputs High Current OutputsExpanded 1/0 1-3 VAC Analog to Digital Converter Ill 19 CPU Expanded Page Expansion of Program Memory Summary Interrupt Routines Expanded MCS-48 System Latch AI? LatchROM IOW Expansion of Data Memory EXPAND!!D MCS-48 System Expansion of Input/Output Read OO-Port #4 Write Port #5 10 or Port #6 Port #7 II AA RD Display Keyboard Expansion Examples See Also Chapter Expanded MCS-48 System Multi-Chip MCS-48 Systems =====ll 8~~5 Memory Bank Switching Port 2 Operations Control Signal SummaryPort Characteristics BUS Port Operations 000 Page Page Instruction SET Instruction SET Subroutines Instruction SET Instruction SET Summary 8021 RET Instruction SET Summary PSW Symbols and Abbreviations UsedDBF ADD A,#data Add Immediate Data to Accumulator ADD A,R r Add Register Contents to AccumulatorADD A,@R r Add Data Memory Contents to Accumulator Addc A,R r Add Carry and Register Contents to Accumulator ANL A,@R r Logical and Accumulator With Memory Mask Addc A,#data Add Carry and Immediate Data to AccumulatorANL A,R r Logical and Accumulator With Register Mask Anld Pp,A Logical and Port 4-7 With Accumulator Mask ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/YANL A,#data Logical and Accumulator With Immediate Mask INC RO Increment REG RET Return to Main Program Andport 4 ContentsWith ACC Bits MOV RO,#50 Move 50DEC to Address 11 00 0 Flag 0 is cleared to zero 10010101111 Contents of the accumulator are cleared to zeroCpla CPL Aacc Contents are COMPLE- Mented to 11010 Flag 1 is cleared to zero F1-0 Overflow to C DA Aacc Adjusted to 00000001 with C SETAC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001 ADD SIX to Bits DEC Rr Decrement Register Not in 8021 Example Decrement contents of external data memory location A,Pp Input Port or Data to Accumulator EN I Enable External InterruptEN Tcnti Enable Timer/Counter Interrupt Not Ento ClK Enable Clock Output Not in 8021,8022 INC @R r Increment Data Memory Location INC a Increment AccumulatorINC Rr Increment Register JC address Jump If Carry Is Set IputoPort 0 Data to Accumulator 8021, 8022 OnlyINS A,BUS Strobed Iput of BUS Data to Accumulator JBb address Jump If Accumulator Bit is Set Not in 8021 JNC address Jump If Carry Is Not Set JF1 address Jump If Flag 1 Is Set Not in 8021JMP address Direct Jump Within 2K Block Jmpp @A Indirect Jump Within JNZ address Jump If Accumulator Is Not Zero JNI address Jump If Interrupt Input is Low Not in 8021Jnto address Jump If Test 0 Is Low Not JNT1 address Jump If Test 1 Is Low Jump to Countroutine Jump to TimerroutineIFTF=1 Jump to Location 53 DEC Mev A, #data Move Immediate Data to Accumulator MaV A,PSW Move PSW Contents to Accumulator Not in 8021MaV A,R r Move Register Contents to Accumulator MaV A,@R r Move Data Memory Contents to Accumulator Mev A,T Move Timer/Counter Contents to Accumulator MaV @Rr,A Move Accumulator Contents to Data Memory Movp A,@A Move Current Page Data to Accumulator Movo A,Pp Move Port 4-7 Data to AccumulatorMovo Pp,A Move Accumulator Data to Port Current page are Moved to ACC Maxdm Movx A,@R1 Move Contents of LocationMOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022 Not in 8021 ORL A,#data Logical OFJ Accumulator With Immediate Mask NOP The NOP InstructionORL A,Rr Logical or Accumulator With Register Mask ORL A,@Rr Logical or Accumulator With Memory Mask 8021 Outl Pp,A Output Accumulator Data to Port 1 or Retr Return With PSW Restore Not in 8021 Contains Rrnc RR Anew ACC Contents areExample Assume carry is not set and accumulator contains Rrtc RRC a Carry is SET and ACC 48 HEX SEL MBO Select Memory BankJMP $+20 Jump to Location BIT 3 is SET REG 7=8 Stop Tcnt Stop Timer/Event-Counter10110101011 Jump to Routine Intif ACe Swap a Swap Nibbles Within Accumulator Strt T Start TimerStrt CNT Start Event Counter Xchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data XCH A,R r Exchange Accumulator-Register ContentsXCH A,@R r Exchange Accumulator and Data Memory Contents XRL A,#data Logical XOR Accumulator With Immediate Mask XRL A,@R1 Xoracc Contents with Mask LocationXRL A,Rr Logical XOR Accumulator With Register Mask XRL A,@Rr Logical XOR Accumulator With Memory Mask Appli~ation Examples Page Driving from External Source Crystal Oscillator ModeLC Oscillator Mode Introduction Application Examples Reset ~~J Rvv-i T1 Multiple Interrupt Sources Ii6 Tf ~r 17&A3 Serves as address latchTt-2 A7 ROM Xtali Both 1/0 and RAM are addressed as data memory =!-39TO F1L This configuration is explained in sectionReset Expander Pinnumbers are Different for ~fd...L DB6 r ~1~ Adding 8 Input Lines ·15 Application Examples Adding Output for KEYBOARD/DISPLAY Scanning RT T T T T JfL Substitute a Application Examples Emulator Circuit DESCRIPTION-6 MHZ Interface to Drum Printer II Keyboard Display TimerRAM Microwave Oven Controller Double Store Double ADDDouble Subtract Double Load Double Right Arithmetic Shift Application Examples Double ExchangeDouble Left Logical Shift Double Right Logical Shift Interrupt Handling Application Examples Binary Multiply 2sCOMPLEMENT and ADD Application Examples Byte Processing SystemR1,A CPL Subtract Second from First INC See AP-49 8 MULTIPLY-ASSEMBLED by MCS-48 Macro Assembler IIn ·1 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-49 APP\,JCATION Examples 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49 Page MCS-4STMComponent Page IIH!T Hmos Single Component 8-BIT Microcomputer Program store enable. This Used to enable data ontoAddress latch enable. This Signal occurs once during S04SH/S04SH-1 /S035HL-1/S035H L-1 Absolute Maximum RATINGS· Inter 8048H/8048H-1/8035HL/8035HL.1 BUS Timing AS a Function of TCY Port 2 Timing 8035HL S04SH/S04SH-1/S035HL/S035HL-1Waveforms Read From External Data Memory J3 Xtal Z 8048H/8048H·1/8035HL/8035HL·1 Rll PIN Configuration Logic Symbol Block Diagram Block Diagram PIN Configuration Logic Symbol PIN Description 8048/8035L/8748/8748-6/8748-8/8035/8035-8 AFN-Q1354A-03 Output Low Voltage 10L = 1.8 mA All Except XTAL1, XTAL2, ResetInput High Voltage X1, X2, RESEi VOL =2.0 mA ===i---h·1 Characteristics Port 2 Timing PROGRAMMING, VERIFYING, and Erasing the 8748 Eprom Crystal Oscillator ModeLC Oscillator Mode Driving from External Source TA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ± PROMPT-48 Microcomputer Design Aid, or Waveforms for ProgrammingVerify .I.~---PROGRAM Intel Corporation 108048/8748/8035L 108048/8748/8035L BUSP1, P2BUS, P1, P2 Operating CharacteristicsIDS0481S7481S035L Absolute Maximum RATINGS· PSEN, RD to Data TAW Address Setup to WR260 TAD Address Setup to Data TOR Data Hold TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV CharacteristicsTop Port Control Setup Before Failing Edge of Prog TpL Port 2 I/O Data Setup Prog Crystal Oscillator Mode Driving from External SourceReset +-----t XTALl TA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ± TA =25C ± 5C, Vee =5V ± 5%, Vee =25V ± PROMPT-48 Microcomputer Design Aid. or Waveforms for Programming Inter Programming Verification Lcoscillator ModeVoo EA Program or Verify Voltage High Level 21.5 24.5 8748 IPHUnit Test Conditions Voo Program Voltage High Level 24.0 2S.0 M8048/M8748/M8035L EA 5 M8048/M8748/M8035L Prog Pin # TLP Port 2 1/0 Data Hold 120 Tcp Port Control Setup Before FallingTpL Port 2 1/0 Data Setup Tpo Output Data Hold Time Tpp Prog Pulae Width ALE JI ~----r---I L Characteristics BUS, P1, P2 AN D Operati NG Characteristics Inter 80411803118031 8049/8039 Symbol Parameter Min Max Unit Operating Characteristics ALE JIL --------..1.--1----L Mask Programmable ROM External ROM or Eprom MHz Operation 18049/8039 INr Til IntJ18049/8039 BUS, RD, WR, PSEN, ALE VOH1 VIH1BUS, RD, WR, PSEN, ALE VOL2 Waveforms TAFC--1 I~OATING-I t=t or Unit Conditions Note Output Data Setup Time 230Port 2 1/0 Data Setup 300 TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OV XT AL1 Crystal Oscillator Mode LC Oscillator Mode 8021 PIN Configuration Logic Symbol Block Diagram T1, RESEl OC to 70CV1Hl Input High Voltage Xtal 1 & 2, T1 VIH10% Input high voltage all except Xtal 1 XTAL2 ALE 8022 Varef ANO,AN1 ALE Xtal Reset AvssProg POO-P07 VTH Fzx 8022 Port 2 Timing IpAL---ooj·1 Analog Input Timing AID Converter Characteristics CNT Analog Input 0, Analog Input TimerMnemonic for in-page Operation Inter GND PIN Description Absolute Maximum Ratings ~~x 125 P20-P23 -- .....--X..... ...Jr 14P52 108243 GND 18243 18243 Tes 1 2 3 4 5 6 7 8 9 10 11 12 # pins= 60 mA-+- 8 mA/pin = 7.5= Output Expander Timing 16,384·8IT ROM with Ready ResetCE1 CE2 ILO Symbol Parameter MIN MAX8355/8355-2 III Cl ~ +- Al ~ 8355/8355·2 Input ModeOutput Mode Directly Compatible with SOS5A CPU PIN Configuration Block Diagram PROG/CE1 8755A8755AFUNCTIONAL PIN Definition UPP UP2121 SA Programming Module Cross Reference Module Name USE withUPP UPPI41 Ready Hold Time Symbol Parameter MIN MAX VIL8755A Comment Prom Read, 1/0 Read and Write Timing Clock Specification for 8755A Wait State Timing Ready =0 Voo Programming Voltage during Write To Eprom Specification ProgrammingITA =OC to 70C Vee =5V ± 5% Vss =OV Program Mode Timing Diagram 8156-2 Enable8085A 8085A-2 8155-2 8155/8156 PIN Functions Timer OUT8155/8156/8155-2/8156-2 8156 Internal Registers Description Reading the Status Register Programming Command Register STB Control Input Mode Output ModeINPUT/OUTPUT Section BFLowLow INTRLowHigh Pca 8155/8156/8155-2/8156-2 Timer Section Example Program WR AD ALE 8085A Minimum System ConfigurationInterval Timer Interrupt Levels Symbol Parameter MIN MAX Units Test Conditions VIL MIN MAX Units Symbol Parameter Write Cycle Read Cycle WI\ J / j 8155/8156/8155-2/8156-2 Basic Output Mode Basic Input Mode PIN Names PIN Configuration Block Diagram Truth Table for Control and Data BUS PIN Status Truth Table for Power Down and Function Enable8185/8185-2 Operational Description Comment Absolute Maximum Ratings 8185/8185-2 Page Page SINGLE-COMPONENT 8-BIT Microcomputer 8051 CPU Architecture 0INTRODUCTION8051 Family MACRO-VIEW of the 8051 Architecture 21/0 Facilities ON-CHIP Peripheral Functions1Interrupt System 8031/8051/8751 8031/8051/8751 3Timer/Event Counters 4Serial Communications 8031/8051/8751 ~=- J~~====~ ~DATA Circuit ground potential 8031/8051/8751 Family Development System and Software Support PsenXTAL1 XTAL2 Insite Library Symbol Parameter Min Typ Max UnitsUniversal Prom Programmer Personality Card UPP-851 Workshop 12MHz Clock Data Memory Write Cycle 8051 Instruction SET Summary Inter8031/8051/8751 All mnemonics copyrlghted@ Intel Corporation InterPage Compatible MCS-48 Components 1024 X 4 BIT Static RAM PIN Configuration 2114A Family Unit Symbol ParameterAddress -..II-------------i--l Normauzed Access Time VS Supply Voltage Typical D.C. and .A.C. Characteristics 2316E 16K 2K 8 ROM 2316E Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI PIN Connection During Read or Program PIN Configuration Nco and A.C.OPERATING Conditions During Read BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10%Operating Characteristics Family VIN = OV Address to Output Delay2708·1 limits 2708·6Limits Units Input Capacitance Waveforms Family PIN Names PIN Configuration Mode Selection CE = VIH. OE = VIL Programming Cout 2716 Typical 16K Eprom System 2716 Device Operation 2716 Industry Standard Pinout . .. Jedec Approved8086·2 MPU .. .Zero Wait State Two Line Control 8205 Ei==~ fEH2·E3 Eii-+-IH-+t-t r A13 --..,-H+-q E8205 Applications State Decoder Circuit MIN MAX Typical Characteristics\.. ~ ~ TA = O·Cto + 75·C, Vee = 5V ± 5% Test Waveforms Switching CharacteristicsCharactristics Conditions of Test Test Load DB ---------- -- +i PIN Configuration Logic DiagramIT os GD ~s ------- + H IE D Functional DescriptionIl D +-+1 DS2 , ------,----.J Basic Schematic SymbolsII. Gated Butter 3-State Gated Buffer 8212 VI. Output Port With Hand-Shaking Here the 8212 is used as the status latch for an 8080A CLR AD2Bossa AD4 AD5 AD6 AD7 ~DI, Stbdo LOW Order IOL = 15mA 8212Output Currents 100mA Input Load Current, ACK, OS2, CR VF = A5V Ili Ffi DOs Output Capacitance 8pF Switching CharacteristicsTyp. Max CIN 051 MD Input Capacitance 9pF 12pF 052. CK. ACK. DI1-Dls Input Capacitance 5pF TCI SGS II,D Icex 821413214 Capacitances 8214/3214 Test Conditions Test Load Circuit Inte 001 ·BITPARALLEL Bidirectional BUS Driver Control aatlng OlEN, CS Bidirectional Driver OUT O---T Waveforms Characteristics Voli VOL2 IFI IF2 IRI IR2 VIL VIH Applications of the 8216/8226 821618226 VCC 8282/8283Octal Latch 010 PinD.scrlptlon PIN Definitions Operational Description Tehoz VOL VOHTivov Tshov JJ\~ J/~~ 8282/8283 Vee Intel Bo- B7 Ao-A7 Characteristics for 8286/8287 Jk~ Output Delay vs. Capacitance Output Page Page Synchronous 5·8 Bit Characters Synchronous and Asynchronous Operation Features and Enhancements Iofl CapacitanceCapacitance pF Input Waveforms for AC Tests Bus Parameters !Note MIN MAX Unit Programmable Interval Timer VIIi -.,--.,q General Control Word Register System Interface Control Word Format Operational DescriptionGeneral Programming 825318253·5 =41 I---t--n --+ Mode 2 Rate Generator MSB 8253/8253-5LSB Reading While Counting Read Operation ChartMode Register for Latching Count Read Operations Oe to 700 e Write Timing Bus Parameters NoteInput Waveforms for A.C. Tests Re.dCycle Clock and Gate Timing 825318253·5 Programmable Peripheral Interface PIN Configuration 8255A Block Diagram Face peripheral devices or structures 8255A18255A·58255A Functional Description 8255A Basic Operation Ports A, B, and C PIN Configuration PIN Names8255A18255A·5 Group a and Group B Controls 8255A Operational Description Mode SelectionSingle Bit Set/Reset Feature Interrupt Control Functions Operating Modes Mode 0 Configurations Mode 0 Port Definition PA7·pAo 8255AJ8255A·5 II I I I, I0 I0 I0 Intr Interrupt Request Input Control Signal DefinitionTPH IBF Input Buffer Full F/F Inte B Output Control Signal Definition10 I ·IOMXlXl Intea Input Operations Combinations of ModeBidirectional Bus 1/0 Control Signal Definition Output Operations LtAOi 8255.Al8255A·5 \, I, erXtJ I0\ ErXtJ I 0\ Only Mode Definition Summary30AFN-00744A-14 Printer Interface Applications of the 8255A MSB PC, r Capacitance MIN. MAX Unit Read CIR TRIT LtR1Bj TwB SIB-Ii SP/EN Programmable Interrupt Controller 8259A Basic Functional Description 8259AInterrupts in Microcomputer Systems INT Interrupt Interrupt Request Register IRR and IN·SERVICE Register ISRPriority Resolver Interrupt Mask Register IMR Interrupt Sequence 8259A8259A Interface to Standard System Bus Cascade BUFFER/COMPARATOR ~O ~ ~ Input Operation Read Disable FunctionProgramming the 8259A General Initialization Command Word 3 ICW3 Initialization Command Words 1 and 2 ICW1,ICW2 8259A 0 I 0 I 0 I 0 I 0 lID, liD, lIDo Ocwa Operation Command Words OCWsOperation Control Word 1 OCW1 Operation Control Word 2 OCW2 Operation Control Words Ocwi R,-r-- I-i-Ioo r,-r,-r Operation Command Word FormatOJNTl Special Fully Nested Mode Special Mask ModeBuffered Mode Fully Nested Mode Wol Word enabled onto the data bus during m5 isAutomatic END of Interrupt Aeoi Mode Rotating Priority Mode B Rotation by Software OH-++-+ Priority Cell Simplified Logic DiagramLevel Triggered Mode This mode is programmed using bit 3 in ICW1 8272 Description Features8272 Registers CPU Interface 8272 Reset to the Interrupt signal Polling Feature IntJ Command SET Read Data Command Descriptions Transfer Capacity EN End of Cylinder Flag No No Data Flag Write Data Readid Write Deleted DataRead Deleted Data Read a Track Scan Commands Sense Drive Status RecalibrateSense Interrupt Status Specify Usa Status Registers BIT Name Symbol Description VIN=OV DC CharacteristicsVIL CLK & WR CLK VIH CINI» ICY ~-----~---V Timing Measurement Conditions Sel-I Block Oiagram LI3 Brief Description of HDLC/SDLC Protocols 8273, 8273·4, 8273·8 Flag DET 32XCLi RAM Programmable KEYBOARD/DISPLAY Interface Principles of Operation 827918279-5Hardware Description 827918279·5 Software Operation Data Write End Interrupt/Error Mode SetStatus Word Data Read Scanned Keyboard Mode, 2·Key Lockout Interface Considerations ===~ Applications General Block Diagram IIL1 Symbol Test TYP MAXVIL2 BUS Parameters Input Waveforms for A.C. Tests 8279 Display Waveforms Scan Timing Scan Waveforms Gpib TALKER/LISTENER 8291 General Description System Diagram8291 General Purpose Interface BUS Gpib Ppas AcdsPacs Acrs DAC SH,AH,T,TE,L,LE,SR,RL,PP,CAH,C Remote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DAB END Remote Messages Sent ATN DABDAC DAV DontCare All Write Registers Interrupt Registers SPAS---SPAS Spasc Llcno LLO Lloc Menting this feature, with 80 and Bi enabied from ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi Section on Parallel Poll Protocol Command Pass Through RegisterProvided for Auxiliary Commands Auxiliary Mode Register Auxiliary Register B Internal Counter2NF Auxiliary Register a Parallel Poll Protocol Reset Procedure 8291 Using DMA 8291 to 8291A Software Compatibility Iloh Device Electrical CharacteristicsVOH-INT Ilol Timing Waveforms TwA~ Gpib Timingsii Figure A.1 State Diagrams next Modified State Diagrams 101 TE,L,LE,C,CE Settling Time for Multiline Messages 21stResponse to ATN 200ns Interface Message Accept Time t Appendix C Figure C-l -Wire Handshake Timing at Figure C.2. Handshake Flowchart 105 IIIL---,--11 ,--I 106 Gpib Controller Ai1W Gpib Transceiver OATA1 EOIBUS1 BUS9 NDAC* I/O Mode 0 PIN Description=OV Gpib Ieee Gpib NrfoTIL Ndac Mode 1 PIN DescriptionMode 2 PIN Description Ieee Nrfd Mode 3 PIN Description LIEN R1L TiR1 Capacitance Operating Characteristics8293 Absolute Maximum Ratings ·118 CharacteristicsTA = O·Cto 70·C Vee= 5.0V ± 10% GND = OV TYP.· MAX Output Loading Test Circuits Waveforms 8293 8294 ·122 8295 123 ====J UPI·41A Features Enhancements Data Moves Signal DescriptionMnemonic Description Bytes Cycles 8041 Al8641 Al8741 a IU1 VIU Write OPERATION-DATA BUS Buffer Register Input and Output Waveforms for A.C. TestsTypical 8041/8741A Current Read OPERATION-DATA BUS Buffer Register WAVEFORMS-DMA CHARACTERISTICS-PORTCHARACTERISTICS-DMA VOO PROGRAMMING, VERIFYING, and Erasing the 8741A Eprom Vdol Timing Specification for ProgrammingSpecification for Programming 8041Al8641 Al8741A Program Support Products Page Credit Microcomputer Development System 10-2 MODEL225 Functional Description Control InterMODEL225 System ComponentsIntegral CRT Peripheral Interface Specifications 9800292 Notavailable on bus110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp 9800556Page Intellec Prompt MCS·48 Microcomputer Design AID Single Component Compu.ter Intellec Prompt Features Intellec Prompt Prompt 48 Commands and Functions MCS-48 Processors Intellec Prompt Functional Description Cycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1% User Interrupt causes an Interrupt only IfPrompt system Is running a user program Ordering Information MCS·48 IN·CIRCUIT Emulator ICE·49 ~ L · GO from .START Till XDATA. Rslt Written Memory Mapping ISIS·II ICE·49 EM1 Emulation Board EM1 MDS·EM1 EM1 SpecificationsDC Power Vcc5V ±5% Icc 300 mA max Ordering Information EM2 Emulation Board AN1 40·PIN Socket Configuration EM2 Block DiagramEM2 ANO MDS-EM2 EM2UPP-1P3 September Canadian Sales Offices TAvnet Electronics McCormick Avenue Costa Mesa Canadian Distributors IntJ International DISTRIBUTORS/REPRESENTATIVES Bowers Avenue International Sales and Marketing Offices INTEL$ Marketing Offices International Sales and Marketing Offices Canadian Service Offices