Page
September
MCS-48 Family of Single Chip Microcomputers Usersmanual
Prompt
BXP
Multibus
Credit
Table of Contents
8051/8751/8031 Microcomputer
Chapters
Packing Information
Emulation Board
Emulation Board 10-19 UPP-103 Universal Prom Programmer
Insite UsersLibrary
Page
Ntroduction
Page
Introduction to MCS-48
5.0 and 10.0 J,Lsec Cycle Versions
Introduction
8021 is code compatible but not pin compatible with
Til
Introduction
Eprom
Introduction
Accumulator
Function of a Computer
Typical Computer System
Architecture of a CPU
Program Counter Jumps, Subroutines and the Stack
Arithmetic/Logic Unit ALU
Three levels of subroutines may be ac- commodated
Instruction Register and Decoder
Address Registers
Instruction Fetch
Control Circuitry
Computer Operations
Timing
Input/Output
Memory Write
Interrupts
To the next instructions
When finished the processor continues on
MOV R2, #05
Step No. Hex Code Assembly Code MOV RO, #32
Our machine language program then becomes
Step Hex Code
Cpla ADD A, REG
ADD A, # ALFA*BETA/2
SUB R7
Function Definition
Hardware Configuration
Developing An MCS-48 Based Product
Education
Prompt
Production
Intellec Development System
Page
Single Component MCS-4S S~stem
Page
Architecture
Summary
Arithmetic Section
~BUS
Location
Single Component System
Input/Output
Single Component System
Single Component System
Pointer
R23
+--1 R
Jump Conditions
Interrupt Timing
Oscillator
As a Timer
As an Event Counter
Clock and Timing Circuits
ALE --f---+--+
Instruction
111
LOVI
BUS PCO·7
Power Down Mode
RUN Stop
Pin Description
Number Function
00-07
Designation
Prog
Programming, Verifying and Erasing Eprom
Reset
Single Component System
Disabling Internal Program Memory
Reset
Test and Debug
Single Step
Reading Internal Program Memory
Following is a functional description of the major elements
Program Memory
Oscillator and Clock
Timer/Event Counter
QUASI-BIDIRECTIONAL Port Structure
Input/Output Capabilities
High Current Outputs
1 T1 Input
Expanded I/O
Jump Test Condition Instructions Accumulator
Reset
Carry Flag Timer Overflow Flag
10 CPU
Program Memory
Functional Specifications
Data Memory
See the 8021 description, .8, for a com- plete explanation
15Timer/Event Counter
Oscillator and Clock
Port 0 Comparator Inputs
Expanded 1/0
High Current Outputs
Test and Interrupt Inputs
1-3 VAC
Analog to Digital Converter
Ill
19 CPU
Expanded
Page
Expansion of Program Memory
Summary
Interrupt Routines
Expanded MCS-48 System
ROM
AI? Latch
Latch
IOW
Expansion of Data Memory
EXPAND!!D MCS-48 System
Expansion of Input/Output
Read OO-Port #4 Write Port #5 10 or Port #6 Port #7
II AA
RD Display
Keyboard
Expansion Examples See Also Chapter
Expanded MCS-48 System
Multi-Chip MCS-48 Systems
=====ll 8~~5
Memory Bank Switching
Port 2 Operations
Control Signal Summary
Port Characteristics
BUS Port Operations
000
Page
Page
Instruction SET
Instruction SET
Subroutines
Instruction SET
Instruction SET Summary
8021
RET
Instruction SET Summary
DBF
Symbols and Abbreviations Used
PSW
ADD A,#data Add Immediate Data to Accumulator
ADD A,R r Add Register Contents to Accumulator
ADD A,@R r Add Data Memory Contents to Accumulator
Addc A,R r Add Carry and Register Contents to Accumulator
ANL A,R r Logical and Accumulator With Register Mask
Addc A,#data Add Carry and Immediate Data to Accumulator
ANL A,@R r Logical and Accumulator With Memory Mask
ANL A,#data Logical and Accumulator With Immediate Mask
ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/Y
Anld Pp,A Logical and Port 4-7 With Accumulator Mask
INC RO Increment REG RET Return to Main Program
Andport 4 Contents
With ACC Bits
MOV RO,#50 Move 50DEC to Address
11 00 0 Flag 0 is cleared to zero
10010101111 Contents of the accumulator are cleared to zero
Cpla CPL Aacc Contents are COMPLE- Mented to
11010 Flag 1 is cleared to zero F1-0
Overflow to C
DA Aacc Adjusted to 00000001 with C SET
AC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001
ADD SIX to Bits
DEC Rr Decrement Register Not in 8021
Example Decrement contents of external data memory location
A,Pp Input Port or Data to Accumulator
EN I Enable External Interrupt
EN Tcnti Enable Timer/Counter Interrupt Not
Ento ClK Enable Clock Output Not in 8021,8022
INC Rr Increment Register
INC a Increment Accumulator
INC @R r Increment Data Memory Location
JC address Jump If Carry Is Set
IputoPort 0 Data to Accumulator 8021, 8022 Only
INS A,BUS Strobed Iput of BUS Data to Accumulator
JBb address Jump If Accumulator Bit is Set Not in 8021
JNC address Jump If Carry Is Not Set
JF1 address Jump If Flag 1 Is Set Not in 8021
JMP address Direct Jump Within 2K Block
Jmpp @A Indirect Jump Within
JNZ address Jump If Accumulator Is Not Zero
JNI address Jump If Interrupt Input is Low Not in 8021
Jnto address Jump If Test 0 Is Low Not
JNT1 address Jump If Test 1 Is Low
Jump to Countroutine
Jump to Timerroutine
IFTF=1
Jump to Location 53 DEC
Mev A, #data Move Immediate Data to Accumulator
MaV A,PSW Move PSW Contents to Accumulator Not in 8021
MaV A,R r Move Register Contents to Accumulator
MaV A,@R r Move Data Memory Contents to Accumulator
Mev A,T Move Timer/Counter Contents to Accumulator
MaV @Rr,A Move Accumulator Contents to Data Memory
Movo Pp,A Move Accumulator Data to Port
Movo A,Pp Move Port 4-7 Data to Accumulator
Movp A,@A Move Current Page Data to Accumulator
Current page are Moved to ACC
Maxdm Movx A,@R1 Move Contents of Location
MOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022
Not in 8021
ORL A,#data Logical OFJ Accumulator With Immediate Mask
NOP The NOP Instruction
ORL A,Rr Logical or Accumulator With Register Mask
ORL A,@Rr Logical or Accumulator With Memory Mask
8021
Outl Pp,A Output Accumulator Data to Port 1 or
Retr Return With PSW Restore Not in 8021
Contains
Rrnc RR Anew ACC Contents are
Example Assume carry is not set and accumulator contains
Rrtc RRC a Carry is SET and ACC
48 HEX
SEL MBO Select Memory Bank
JMP $+20
Jump to Location
BIT 3 is SET REG 7=8
Stop Tcnt Stop Timer/Event-Counter
10110101011
Jump to Routine Intif ACe
Strt CNT Start Event Counter
Strt T Start Timer
Swap a Swap Nibbles Within Accumulator
XCH A,@R r Exchange Accumulator and Data Memory Contents
XCH A,R r Exchange Accumulator-Register Contents
Xchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data
XRL A,#data Logical XOR Accumulator With Immediate Mask
XRL A,@R1 Xoracc Contents with Mask Location
XRL A,Rr Logical XOR Accumulator With Register Mask
XRL A,@Rr Logical XOR Accumulator With Memory Mask
Appli~ation Examples
Page
Driving from External Source
Crystal Oscillator Mode
LC Oscillator Mode
Introduction
Application Examples
Reset
~~J
Rvv-i T1
Multiple Interrupt Sources
Ii6
Tf ~r
Tt-2 A7
Serves as address latch
17&A3
ROM
Xtali
Both 1/0 and RAM are addressed as data memory
=!-39TO
Reset
This configuration is explained in section
F1L
Expander
Pinnumbers are Different for
~fd...L
DB6 r
~1~
Adding 8 Input Lines
·15
Application Examples
Adding Output for KEYBOARD/DISPLAY Scanning
RT T T T T
JfL
Substitute a
Application Examples Emulator Circuit DESCRIPTION-6 MHZ
Interface to Drum Printer
RAM
Timer
II Keyboard Display
Microwave Oven Controller
Double Store
Double ADD
Double Subtract
Double Load
Double Right Arithmetic Shift
Application Examples Double Exchange
Double Left Logical Shift
Double Right Logical Shift
Interrupt Handling
Application Examples Binary Multiply
2sCOMPLEMENT and ADD
Application Examples Byte Processing System
R1,A
CPL Subtract Second from First INC
See AP-49
8 MULTIPLY-ASSEMBLED by MCS-48 Macro Assembler
IIn ·1
16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-49
APP\,JCATION Examples
16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49
Page
MCS-4STMComponent
Page
IIH!T
Hmos Single Component 8-BIT Microcomputer
Program store enable. This
Used to enable data onto
Address latch enable. This
Signal occurs once during
S04SH/S04SH-1 /S035HL-1/S035H L-1
Absolute Maximum RATINGS·
Inter 8048H/8048H-1/8035HL/8035HL.1
BUS Timing AS a Function of TCY
Port 2 Timing
8035HL
S04SH/S04SH-1/S035HL/S035HL-1
Waveforms
Read From External Data Memory
J3 Xtal Z
8048H/8048H·1/8035HL/8035HL·1
Rll
PIN Configuration Logic Symbol Block Diagram
Block Diagram
PIN Configuration Logic Symbol
PIN Description
8048/8035L/8748/8748-6/8748-8/8035/8035-8
AFN-Q1354A-03
Output Low Voltage 10L = 1.8 mA
All Except XTAL1, XTAL2, Reset
Input High Voltage X1, X2, RESEi
VOL =2.0 mA
===i---h·1
Characteristics Port 2 Timing
PROGRAMMING, VERIFYING, and Erasing the 8748 Eprom
Crystal Oscillator Mode
LC Oscillator Mode
Driving from External Source
TA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ±
Verify .I.~---PROGRAM
Waveforms for Programming
PROMPT-48 Microcomputer Design Aid, or
Intel Corporation
108048/8748/8035L
108048/8748/8035L
BUSP1, P2BUS, P1, P2
Operating Characteristics
IDS0481S7481S035L
Absolute Maximum RATINGS·
PSEN, RD to Data
TAW Address Setup to WR
260 TAD Address Setup to Data
TOR Data Hold
TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV
Characteristics
Top Port Control Setup Before Failing Edge of Prog
TpL Port 2 I/O Data Setup
Prog
Crystal Oscillator Mode Driving from External Source
Reset
+-----t XTALl
TA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ±
TA =25C ± 5C, Vee =5V ± 5%, Vee =25V ±
PROMPT-48 Microcomputer Design Aid. or
Waveforms for Programming
Inter
Voo
Lcoscillator Mode
Programming Verification
EA Program or Verify Voltage High Level 21.5 24.5 8748
IPH
Unit Test Conditions
Voo Program Voltage High Level 24.0 2S.0
M8048/M8748/M8035L
EA 5
M8048/M8748/M8035L
Prog
Pin #
TLP Port 2 1/0 Data Hold 120
Tcp Port Control Setup Before Falling
TpL Port 2 1/0 Data Setup
Tpo Output Data Hold Time Tpp Prog Pulae Width
ALE JI ~----r---I L
Characteristics
BUS, P1, P2
AN D Operati NG Characteristics
Inter
80411803118031
8049/8039
Symbol Parameter Min Max Unit
Operating Characteristics
ALE JIL --------..1.--1----L
Mask Programmable ROM External ROM or Eprom MHz Operation
18049/8039
INr
Til
IntJ18049/8039
BUS, RD, WR, PSEN, ALE VOH1
VIH1
BUS, RD, WR, PSEN, ALE
VOL2
Waveforms
TAFC--1 I~OATING-I t=t or
Unit Conditions Note
Output Data Setup Time 230
Port 2 1/0 Data Setup 300
TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OV
XT AL1
Crystal Oscillator Mode LC Oscillator Mode
8021
PIN Configuration Logic Symbol Block Diagram
T1, RESEl
OC to 70C
V1Hl Input High Voltage Xtal 1 & 2, T1
VIH10% Input high voltage all except Xtal 1
XTAL2
ALE
8022
Varef ANO,AN1 ALE Xtal
Reset Avss
Prog POO-P07
VTH
Fzx
8022
Port 2 Timing
IpAL---ooj·1
Analog Input Timing
AID Converter Characteristics
Mnemonic for in-page Operation
Analog Input 0, Analog Input Timer
CNT
Inter
GND
PIN Description
Absolute Maximum Ratings
~~x
125
P20-P23 -- .....--X..... ...Jr
14P52
108243
GND
18243
18243
Tes
1 2 3 4 5 6 7 8 9 10 11 12
# pins= 60 mA-+- 8 mA/pin = 7.5=
Output Expander Timing
16,384·8IT ROM with
Ready
Reset
CE1
CE2
ILO
Symbol Parameter MIN MAX
8355/8355-2
III
Cl ~
+- Al ~
Output Mode
Input Mode
8355/8355·2
Directly Compatible with SOS5A CPU
PIN Configuration Block Diagram
8755AFUNCTIONAL PIN Definition
8755A
PROG/CE1
UPP UP2121
SA Programming Module Cross Reference Module Name USE with
UPP
UPPI41
Ready Hold Time
Symbol Parameter MIN MAX VIL
8755A
Comment
Prom Read, 1/0 Read and Write Timing
Clock Specification for 8755A
Wait State Timing Ready =0
ITA =OC to 70C Vee =5V ± 5% Vss =OV
Specification Programming
Voo Programming Voltage during Write To Eprom
Program Mode Timing Diagram
8156-2
Enable
8085A 8085A-2
8155-2
8155/8156/8155-2/8156-2
Timer OUT
8155/8156 PIN Functions
8156 Internal Registers
Description
Reading the Status Register
Programming Command Register
STB
Control Input Mode Output Mode
INPUT/OUTPUT Section
BFLowLow INTRLowHigh
Pca
8155/8156/8155-2/8156-2
Timer Section
Example Program
Interval Timer Interrupt Levels
8085A Minimum System Configuration
WR AD ALE
Symbol Parameter MIN MAX Units Test Conditions VIL
MIN MAX Units
Symbol Parameter
Write Cycle
Read Cycle
WI\ J / j
8155/8156/8155-2/8156-2
Basic Output Mode
Basic Input Mode
PIN Names
PIN Configuration Block Diagram
Truth Table for Control and Data BUS PIN Status
Truth Table for Power Down and Function Enable
8185/8185-2
Operational Description
Comment
Absolute Maximum Ratings
8185/8185-2
Page
Page
SINGLE-COMPONENT 8-BIT Microcomputer
8051 CPU Architecture
0INTRODUCTION
8051 Family
MACRO-VIEW of the 8051 Architecture
1Interrupt System
ON-CHIP Peripheral Functions
21/0 Facilities
8031/8051/8751
8031/8051/8751
3Timer/Event Counters
4Serial Communications
8031/8051/8751
~=- J~~====~
~DATA
Circuit ground potential
8031/8051/8751
Family Development System and Software Support
Psen
XTAL1
XTAL2
Insite Library
Symbol Parameter Min Typ Max Units
Universal Prom Programmer Personality Card UPP-851
Workshop
12MHz Clock
Data Memory Write Cycle
8051 Instruction SET Summary
Inter8031/8051/8751
All mnemonics copyrlghted@ Intel Corporation
Inter
Page
Compatible MCS-48 Components
1024 X 4 BIT Static RAM
PIN Configuration
2114A Family
Address -..II-------------i--l
Symbol Parameter
Unit
Normauzed Access Time VS Supply Voltage
Typical D.C. and .A.C. Characteristics
2316E 16K 2K 8 ROM
2316E
Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI
PIN Connection During Read or Program
PIN Configuration
Nco and A.C.OPERATING Conditions During Read
BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10%
Operating Characteristics
Family
VIN = OV
Address to Output Delay
2708·1 limits 2708·6Limits Units
Input Capacitance
Waveforms
Family
PIN Names
PIN Configuration Mode Selection
CE = VIH. OE = VIL
Programming
Cout
2716
Typical 16K Eprom System
2716
Device Operation
2716
Industry Standard Pinout . .. Jedec
Approved
8086·2 MPU .. .Zero Wait State
Two Line Control
8205
Ei==~ fEH2·E3
Eii-+-IH-+t-t r
A13 --..,-H+-q E
8205
Applications
State Decoder Circuit
MIN MAX
Typical Characteristics
\.. ~ ~
TA = O·Cto + 75·C, Vee = 5V ± 5%
Test Waveforms
Switching Characteristics
Charactristics
Conditions of Test Test Load
DB ---------- -- +i
PIN Configuration Logic Diagram
IT os
GD ~s ------- + H
IE D
Functional Description
Il D
+-+1
DS2 , ------,----.J
Basic Schematic Symbols
II. Gated Butter 3-State
Gated Buffer
8212
VI. Output Port With Hand-Shaking
Here the 8212 is used as the status latch for an 8080A
CLR
AD2
Bossa AD4 AD5 AD6 AD7
~DI, Stbdo LOW Order
IOL = 15mA
8212
Output Currents 100mA
Input Load Current, ACK, OS2, CR VF = A5V
Ili
Ffi
DOs Output Capacitance 8pF
Switching Characteristics
Typ. Max CIN 051 MD Input Capacitance 9pF 12pF
052. CK. ACK. DI1-Dls Input Capacitance 5pF
TCI
SGS
II,D
Icex
821413214
Capacitances
8214/3214
Test Conditions Test Load Circuit
Inte
001
·BITPARALLEL Bidirectional BUS Driver
Control aatlng OlEN, CS
Bidirectional Driver
OUT O---T
Waveforms Characteristics
Voli VOL2
IFI IF2 IRI IR2 VIL VIH
Applications of the 8216/8226
821618226
VCC
8282/8283
Octal Latch
010
PinD.scrlptlon
PIN Definitions Operational Description
Tehoz
VOL VOH
Tivov
Tshov
JJ\~ J/~~
8282/8283
Vee
Intel
Bo- B7
Ao-A7
Characteristics for 8286/8287
Jk~
Output Delay vs. Capacitance
Output
Page
Page
Synchronous 5·8 Bit Characters
Synchronous and Asynchronous Operation
Features and Enhancements
Capacitance pF
Capacitance
Iofl
Input Waveforms for AC Tests
Bus Parameters !Note
MIN MAX Unit
Programmable Interval Timer
VIIi -.,--.,q
General
Control Word Register
System Interface
Control Word Format
Operational Description
General
Programming
825318253·5
=41 I---t--n --+
Mode 2 Rate Generator
LSB
8253/8253-5
MSB
Reading While Counting
Read Operation Chart
Mode Register for Latching Count
Read Operations
Oe to 700 e
Write Timing
Bus Parameters Note
Input Waveforms for A.C. Tests
Re.dCycle
Clock and Gate Timing
825318253·5
Programmable Peripheral Interface
PIN Configuration 8255A Block Diagram
Face peripheral devices or structures
8255A18255A·5
8255A Functional Description
8255A Basic Operation
Ports A, B, and C
PIN Configuration PIN Names
8255A18255A·5
Group a and Group B Controls
Single Bit Set/Reset Feature
Mode Selection
8255A Operational Description
Interrupt Control Functions
Operating Modes
Mode 0 Configurations
Mode 0 Port Definition
PA7·pAo
8255AJ8255A·5
II I I I, I0 I0 I0
Intr Interrupt Request
Input Control Signal Definition
TPH
IBF Input Buffer Full F/F
Inte B
Output Control Signal Definition
10 I ·IOMXlXl
Intea
Input Operations
Combinations of Mode
Bidirectional Bus 1/0 Control Signal Definition
Output Operations
LtAOi
8255.Al8255A·5
\, I, erXtJ I0\
ErXtJ I 0\
30AFN-00744A-14
Mode Definition Summary
Only
Printer Interface
Applications of the 8255A
MSB
PC, r
Capacitance
MIN. MAX Unit
Read
CIR
TRIT LtR1Bj
TwB
SIB-Ii
SP/EN
Programmable Interrupt Controller
Interrupts in Microcomputer Systems
8259A
8259A Basic Functional Description
INT Interrupt
Interrupt Request Register IRR and IN·SERVICE Register ISR
Priority Resolver
Interrupt Mask Register IMR
Interrupt Sequence
8259A
8259A Interface to Standard System Bus
Cascade BUFFER/COMPARATOR
~O ~ ~
Input Operation Read
Disable Function
Programming the 8259A
General
Initialization Command Word 3 ICW3
Initialization Command Words 1 and 2 ICW1,ICW2
8259A
0 I 0 I 0 I 0 I 0 lID, liD, lIDo
Ocwa
Operation Command Words OCWs
Operation Control Word 1 OCW1
Operation Control Word 2 OCW2 Operation Control Words Ocwi
OJNTl
Operation Command Word Format
R,-r-- I-i-Ioo r,-r,-r
Special Fully Nested Mode
Special Mask Mode
Buffered Mode
Fully Nested Mode
Wol
Word enabled onto the data bus during m5 is
Automatic END of Interrupt Aeoi Mode
Rotating Priority Mode B Rotation by Software
OH-++-+
Priority Cell Simplified Logic Diagram
Level Triggered Mode
This mode is programmed using bit 3 in ICW1
8272
Description
Features
8272
Registers CPU Interface
8272
Reset to the Interrupt signal
Polling Feature
IntJ
Command SET
Read Data
Command Descriptions
Transfer Capacity EN End of Cylinder Flag No No Data Flag
Write Data
Readid
Write Deleted Data
Read Deleted Data
Read a Track
Scan Commands
Sense Drive Status
Recalibrate
Sense Interrupt Status
Specify
Usa
Status Registers BIT Name Symbol Description
VIN=OV
DC Characteristics
VIL CLK & WR CLK VIH
CINI»
ICY
~-----~---V
Timing Measurement Conditions
Sel-I
Block Oiagram
LI3
Brief Description of HDLC/SDLC Protocols
8273, 8273·4, 8273·8
Flag DET
32XCLi
RAM
Programmable KEYBOARD/DISPLAY Interface
Hardware Description
827918279-5
Principles of Operation
827918279·5
Software Operation
Data Write
End Interrupt/Error Mode Set
Status Word
Data Read
Scanned Keyboard Mode, 2·Key Lockout
Interface Considerations
===~
Applications
General Block Diagram
VIL2
Symbol Test TYP MAX
IIL1
BUS Parameters
Input Waveforms for A.C. Tests
8279
Display Waveforms
Scan Timing Scan Waveforms
Gpib TALKER/LISTENER
8291
General Description
System Diagram
8291
General Purpose Interface BUS Gpib
Ppas
Acds
Pacs
Acrs
DAC
SH,AH,T,TE,L,LE,SR,RL,PP,C
AH,C
Remote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DAB
END
Remote Messages Sent ATN DAB
DAC
DAV
DontCare
All Write Registers
Interrupt Registers
SPAS---SPAS Spasc Llcno LLO Lloc
Menting this feature, with 80 and Bi enabied from
ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi
Provided for
Command Pass Through Register
Section on Parallel Poll Protocol
Auxiliary Commands
Auxiliary Mode Register
Auxiliary Register B
Internal Counter
2NF
Auxiliary Register a
Parallel Poll Protocol
Reset Procedure
8291 Using DMA 8291 to 8291A Software Compatibility
Iloh
Device Electrical Characteristics
VOH-INT
Ilol
Timing Waveforms
TwA~
Gpib Timingsii
Figure A.1 State Diagrams next
Modified State Diagrams
101
Response to ATN 200ns Interface Message Accept Time t
Settling Time for Multiline Messages 21st
TE,L,LE,C,CE
Appendix C
Figure C-l -Wire Handshake Timing at
Figure C.2. Handshake Flowchart
105
IIIL---,--11 ,--I
106
Gpib Controller
Ai1W
Gpib Transceiver
OATA1
EOI
BUS1
BUS9
NDAC* I/O
Mode 0 PIN Description
=OV
Gpib
TIL
Nrfo
Ieee Gpib
Mode 2 PIN Description
Mode 1 PIN Description
Ndac
Ieee
Nrfd
Mode 3 PIN Description
LIEN
R1L
TiR1
Capacitance
Operating Characteristics
8293
Absolute Maximum Ratings
·118
Characteristics
TA = O·Cto 70·C Vee= 5.0V ± 10% GND = OV
TYP.· MAX
Output Loading Test Circuits
Waveforms
8293
8294
·122
8295
123
====J
UPI·41A Features Enhancements
Mnemonic Description Bytes Cycles
Signal Description
Data Moves
8041 Al8641 Al8741 a
IU1
VIU
Write OPERATION-DATA BUS Buffer Register
Input and Output Waveforms for A.C. Tests
Typical 8041/8741A Current
Read OPERATION-DATA BUS Buffer Register
CHARACTERISTICS-DMA
CHARACTERISTICS-PORT
WAVEFORMS-DMA
VOO
PROGRAMMING, VERIFYING, and Erasing the 8741A Eprom
Specification for Programming
Timing Specification for Programming
Vdol
8041Al8641 Al8741A
Program
Support Products
Page
Credit
Microcomputer Development System
10-2
MODEL225 Functional Description
Control
InterMODEL225 System Components
Integral CRT
Peripheral Interface
Specifications
9800292
Notavailable on bus
110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp
9800556
Page
Intellec Prompt MCS·48 Microcomputer Design AID
Single Component Compu.ter
Intellec Prompt Features
Intellec Prompt
Prompt 48 Commands and Functions
MCS-48 Processors
Intellec Prompt Functional Description
Prompt system Is running a user program
User Interrupt causes an Interrupt only If
Cycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1%
Ordering Information
MCS·48 IN·CIRCUIT Emulator
ICE·49
~ L ·
GO from .START Till XDATA. Rslt Written
Memory Mapping
ISIS·II
ICE·49
EM1 Emulation Board
EM1
MDS·EM1
EM1 Specifications
DC Power Vcc5V ±5% Icc 300 mA max
Ordering Information
EM2 Emulation Board
AN1
40·PIN Socket Configuration EM2 Block Diagram
EM2
ANO
UPP-1P3
EM2
MDS-EM2
September
Canadian Sales Offices
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Canadian Distributors
IntJ
International DISTRIBUTORS/REPRESENTATIVES
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International Sales and Marketing Offices
Canadian Service Offices
