Intel mcs-48 P10-P17 Port P20-27, Pin =, Testable. with conditional, Jump instruction, Active low

intel" S04SH/S04SH-1/S035HL/S035HL-1 ~!ru~[!"o!MlOOO~OOW

PIN DESCRIPTION

Designation

VSS

VDD

VCC

PROG

P10-P17

Port 1

P20-27

Port 2

DBO-DB7

BUS

TO

T1

INT

Pin = Function

20Circuit GND potential

26low power standby pin

40Main power supply; +5V during operation.

25Output strobe for 8243 I/O expander.

27-34 . 8-bit quasi-bidirectional port.

21-248-bitquasi~bidirectional port.

35-38 P20-P23 contain the four high order program counter bits during an external pro- gram memory fetch and serve as a 4-bit I/O expander bus for 8243.

12-19 True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically latched.

Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the control of PSEN. Also contains the address and data during an external RAM data store instruction, under control of ALE, RD, and WR.

Input pin testable using the conditional transfer in- structions JTO and JNTO. TO can be designated as a clock output using ENTO ClK instruction.

39Input pin testable using the JT1, and JNT1 instructions. Can be designated the timer/counter input using the STRT CNT instruction.

6Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is dis- abled after a reset. Also

Designation	Pin =	Function
		testable. with conditional
		jump instruction.
		(Active low)
RD	8	Output strobe activated
		during a BUS read. Can be
		used to enable data onto the
		bus from an external device.
		Used as a read strobe to
		external data memory.
		(Active low)
RESET	4	Input which is used to
		initialize the processor.
		(Active low)
		(Non TTL VI H)
WR	10	Output strobe during a bus
		write. (Active low)
		Used as write strobe to
		external data memory.
ALE	11	Address latch enable. This
		signal occurs once during
		each cycle and is useful as a
		clock output.
		The negative edge of ALE
		strobes address into ex-
		ternal data and program
		memory.
PSEN	9	Program store enable. This
		output occurs only during a

fetch to external program memory. (Active low)

SS5 Single step input can be used in conjunction with ALE to "single step" the processor through each instruction. (Active low)

EA	7	External access input which
		forces all program memory
		fetches to reference external
		memory. Useful for emula-
		tion and debug, and
		essential for testi ng arid
		program verification.
		(Active high)
XTAl1	2	One side of crystal input for
		internal oscillator. Also
		input for external source.
		(Non TTL VI H)
XTAl2	3	Other side of crystal input.

AFN~01491A-02

6-2