Intel mcs-48 manual 40·PIN Socket Configuration EM2 Block Diagram, Ano, AN1

			EM2
40·PIN SOCKET CONFIGURATION			EM2 BLOCK DIAGRAM
P28	Vee
P27	P25
AVec	P24
VAREF	PROD
ANI	P23
ANO	P22	o
AVss	P21
TO	P20
VTH	P17		2048
POO	P18		EPROM
			. ---- r - l MEMORY
POI	P15
P02	P14
P03	P13	4(J.PIN	8755A
P04	P12
		SOCKET
P05	Pll
P08	Pl0		8022 EMULATOR CHIP
P07	RESET
ALE	XTAL2
Tl	XTALI
Vss	SUBST	o PIN 1
		SQUARE SOLDER PAD

PIN DESCRIPTION

Deslg·
nation	Pin II	Function
Vss	20	Circuit GND potential.
Vcc	40	+ 5V circuit power supply.
PROG	37	Output strobe for Intell!> 8243 I/O ex-
		pander.
POO-P07	10-17 8·bit open-drain port with comparator
Port 0		Inputs. The switching threshold is set
		externally by VTH . Optional pull-up reo
		slstors may be added via ROM mask
		selection. (The emulator board has
		switch selection of this option.)
VTH	9	Port 0 threshold reference pin.
P10-P17 25-32 8-bit quasi·bidirectlonalport.
Port 1
P20-P27	33-36	8-bit quasi-bidirectional port.

Deslg·	Function
nation Pin II

RESET 24 Input used to Initialize the processor by clearing status flip-flops and setting the program counter to zero.

AVss 7 A/D converter GND potential. Also establishes the lower limit of the con- version range.

AVcc 3 AID +5V power supply.

SUBST 21 Substrate pin used with a bypass capa- citor to stabilize the substrate voltage and improve AID accuracy.

VAREF 4 AID converter reference voltage. Estab- lishes the upper limit of the conversion range.

Port 2	38-39	P20-P23 also serve as a 4-bit I/O ex-
	1-2	pander for Intell!> 8243.
TO	8 Interrupt input and input pin testable
		using the conditional transfer Instruc-
		tions JTO and JNTO. Initiates an inter-
		rupt following a low level input if inter-
		rupt is enabled. Interrupt Is disabled
		after a reset.
T1	19	Input pin testable using the JT1 and
		JNT1 conditional transfer instructions.
		Can be designated the timer/event

counter input using the STRT CNT in- struction. Also serves as the zero-cross detection input to allow zero-crossover sensing of slowly moving AC Inputs. Optional pull-up resistor may be added via ROM mask selection.

ANO,	6,5	Analog inputs to AID converter. Soft-
AN1		ware selectable on-chip via SEL ANO
		and SEL AN1 instructions.
ALE	18	Address Latch Enable. Signal occur-
		ring once every 30 input input clocks
		(once every single cycle instruction),
		used as an output clock.
XTAL1	22	One side of crystal, inductor, or re-
		sistor input for internal oscillator. Also
		Input for external frequency source.
		(Not TTL compatible.)
XTAL2	23 Other side of timing control element.
		This pin Is not connected when an ex-
		ternal frequency source is used.
10-21		AFN-OOBOOA-02