Intel mcs-48 manual DEC Rr Decrement Register Not in 8021

INSTRUCTION SET

Example: Decrement contents of external data memory location 63.

MOV RO,#3FH	;MOVE '3F'HEX TO REG 0
MOVX A,@RO	;MOVE CONTENTS OF LOCATION 63
	;TO ACC
DEC A	;DECREMENT ACC
MOVX @RO,A	;MOVE CONTENTS OF ACC TO
	;LOCATION 63 IN EXPANDED
	;MEMORY

DEC Rr Decrement Register (Not in 8021, 8022)

1110011rrri

The contents of working register 'r'are decremented by one.

(Rr)-- (Rr)-1r=0-7

Example: DECR1: DEC R1 ;DECREMENT CONTENTS OF REG 1

DIS I Disable External Interrupt (Not in 8021)

10001101011

External interrupts are disabled. A low signal on the interrupt input pin has no effect.

DIS TCNTI Disable Timer/Counter Interrupt (Not in 8021)

10011101011

Timer/counter interrupts are disabled. Any pending timer interrupt request is cleared. The interrupt sequence is not initiated by an overflow, but the timer flag is set and time accumulation continues.

DJNZ Rrl address Decrement Register and Test

11 1 1 0 11 r r r 1 1a7 a6 a5 a4 1a3 a2 a1 ao 1

This is a 2-cycle instruction. Register 'r'is decremented and tested for zero. If the register contains all zeros, program control falls through to the next instruction. If the register contents

are not zero, control jumps to the specified 'address'.

The address in this case must evaluate to 8-bits, that is, the jump must be to a location within the current 256-location page.

(Rr)-- (Rr)-1r=0-7 If Rr not 0

(PCO-7)-- addr

Mnemonics copyright Intel Corporation 1976.

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