10 I ·IOMXlXl, Output Control Signal Definition | Intel mcs-48

8255A18255A·5

Output Control Signal Definition

OBF (Output Buffer Full F/F). The OBF output will go "low" to Indicate that the CPU has written data out to the specified port. The OBF F/F will be set by the rising edge of the WR Input and reset by ACK Input being low.

ACK (Acknowledge Input). A "low" on this Input informs the 8255A that the data from port A or port B has been ac· cepted. In essence, a response from the peripheral device indicating that it has received the data output by the CPU.

INTR (Interrupt Reque,t). A "high" on this output can be used to interrupt the CPU when an output device has ac- cepted data transmitted by the CPU. INTR is set when ACK is a "one", OBF IS a "one" and INTE is a "one". It is reset by the falling edge of WR.

INTEA

Controlled by bit set/reset of PC6.

INTE B

Controlled by bit set/reset of PC2.

	MODE. (PORT AI
		PA,.p....	8
CONTROL WORD
D7 D. Os 04 03 02 0, Do
/. 10 I. 1°1·IOMXlXl	r -- ,
	I INTE	I
L~	I A	JI
O-OUTPUT
WR -
	MODE 1 (PORT BI
		PB1.P~~
CONTROL WORD
		PC,	ODs
			INTRa

Figure 8. MODE 1 Output

r

INTR

...t----tAK

OUTPUT

Figure 9. Mode 1 (Strobed Output)

AFN.Q0744A-'O

Image 341

Intel mcs-48 manual 10 I ·IOMXlXl, Output Control Signal Definition, Intea, Inte B

Contents

Page September MCS-48 Family of Single Chip Microcomputers Usersmanual Multibus BXPCredit Prompt Table of Contents 8051/8751/8031 Microcomputer Chapters Emulation Board 10-19 UPP-103 Universal Prom Programmer Emulation BoardInsite UsersLibrary Packing InformationPage Ntroduction Page Introduction to MCS-48 8021 is code compatible but not pin compatible with Introduction5.0 and 10.0 J,Lsec Cycle Versions Eprom IntroductionTil Introduction Typical Computer System Function of a ComputerArchitecture of a CPU Accumulator Program Counter Jumps, Subroutines and the Stack Instruction Register and Decoder Three levels of subroutines may be ac- commodatedAddress Registers Arithmetic/Logic Unit ALU Computer Operations Control CircuitryTiming Instruction Fetch Interrupts Memory WriteInput/Output To the next instructions When finished the processor continues on Our machine language program then becomes Step No. Hex Code Assembly Code MOV RO, #32Step Hex Code MOV R2, #05 SUB R7 ADD A, # ALFA*BETA/2Cpla ADD A, REG Developing An MCS-48 Based Product Hardware ConfigurationEducation Function Definition Prompt Production Intellec Development SystemPage Single Component MCS-4S S~stem Page Arithmetic Section SummaryArchitecture ~BUS Location Single Component System Input/Output Single Component System Single Component System Pointer R23 +--1 R Jump Conditions Interrupt Timing As an Event Counter As a TimerClock and Timing Circuits Oscillator ALE --f---+--+ Instruction 111 LOVI RUN Stop Power Down ModeBUS PCO·7 Pin Description Designation 00-07Prog Number Function Programming, Verifying and Erasing Eprom Reset Single Component System Test and Debug ResetSingle Step Disabling Internal Program Memory Reading Internal Program Memory Following is a functional description of the major elements Program Memory Oscillator and Clock Timer/Event Counter QUASI-BIDIRECTIONAL Port Structure Input/Output Capabilities Expanded I/O 1 T1 InputHigh Current Outputs Carry Flag Timer Overflow Flag Reset10 CPU Jump Test Condition Instructions Accumulator Data Memory Functional SpecificationsProgram Memory Oscillator and Clock 15Timer/Event CounterPort 0 Comparator Inputs See the 8021 description, .8, for a com- plete explanation Test and Interrupt Inputs High Current OutputsExpanded 1/0 1-3 VAC Analog to Digital Converter Ill 19 CPU Expanded Page Expansion of Program Memory Summary Interrupt Routines Expanded MCS-48 System Latch AI? LatchROM IOW Expansion of Data Memory EXPAND!!D MCS-48 System Expansion of Input/Output Read OO-Port #4 Write Port #5 10 or Port #6 Port #7 II AA RD Display Keyboard Expansion Examples See Also Chapter Expanded MCS-48 System Multi-Chip MCS-48 Systems =====ll 8~~5 Memory Bank Switching Port Characteristics Control Signal SummaryBUS Port Operations Port 2 Operations 000 Page Page Instruction SET Instruction SET Subroutines Instruction SET Instruction SET Summary 8021 RET Instruction SET Summary PSW Symbols and Abbreviations UsedDBF ADD A,@R r Add Data Memory Contents to Accumulator ADD A,R r Add Register Contents to AccumulatorAddc A,R r Add Carry and Register Contents to Accumulator ADD A,#data Add Immediate Data to Accumulator ANL A,@R r Logical and Accumulator With Memory Mask Addc A,#data Add Carry and Immediate Data to AccumulatorANL A,R r Logical and Accumulator With Register Mask Anld Pp,A Logical and Port 4-7 With Accumulator Mask ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/YANL A,#data Logical and Accumulator With Immediate Mask With ACC Bits Andport 4 ContentsMOV RO,#50 Move 50DEC to Address INC RO Increment REG RET Return to Main Program Cpla CPL Aacc Contents are COMPLE- Mented to 10010101111 Contents of the accumulator are cleared to zero11010 Flag 1 is cleared to zero F1-0 11 00 0 Flag 0 is cleared to zero AC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001 DA Aacc Adjusted to 00000001 with C SETADD SIX to Bits Overflow to C DEC Rr Decrement Register Not in 8021 Example Decrement contents of external data memory location EN Tcnti Enable Timer/Counter Interrupt Not EN I Enable External InterruptEnto ClK Enable Clock Output Not in 8021,8022 A,Pp Input Port or Data to Accumulator INC @R r Increment Data Memory Location INC a Increment AccumulatorINC Rr Increment Register INS A,BUS Strobed Iput of BUS Data to Accumulator IputoPort 0 Data to Accumulator 8021, 8022 OnlyJBb address Jump If Accumulator Bit is Set Not in 8021 JC address Jump If Carry Is Set JMP address Direct Jump Within 2K Block JF1 address Jump If Flag 1 Is Set Not in 8021Jmpp @A Indirect Jump Within JNC address Jump If Carry Is Not Set Jnto address Jump If Test 0 Is Low Not JNI address Jump If Interrupt Input is Low Not in 8021JNT1 address Jump If Test 1 Is Low JNZ address Jump If Accumulator Is Not Zero IFTF=1 Jump to TimerroutineJump to Location 53 DEC Jump to Countroutine MaV A,R r Move Register Contents to Accumulator MaV A,PSW Move PSW Contents to Accumulator Not in 8021MaV A,@R r Move Data Memory Contents to Accumulator Mev A, #data Move Immediate Data to Accumulator Mev A,T Move Timer/Counter Contents to Accumulator MaV @Rr,A Move Accumulator Contents to Data Memory Movp A,@A Move Current Page Data to Accumulator Movo A,Pp Move Port 4-7 Data to AccumulatorMovo Pp,A Move Accumulator Data to Port MOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022 Maxdm Movx A,@R1 Move Contents of LocationNot in 8021 Current page are Moved to ACC ORL A,Rr Logical or Accumulator With Register Mask NOP The NOP InstructionORL A,@Rr Logical or Accumulator With Memory Mask ORL A,#data Logical OFJ Accumulator With Immediate Mask 8021 Outl Pp,A Output Accumulator Data to Port 1 or Retr Return With PSW Restore Not in 8021 Example Assume carry is not set and accumulator contains Rrnc RR Anew ACC Contents areRrtc RRC a Carry is SET and ACC Contains JMP $+20 SEL MBO Select Memory BankJump to Location 48 HEX 10110101011 Stop Tcnt Stop Timer/Event-CounterJump to Routine Intif ACe BIT 3 is SET REG 7=8 Swap a Swap Nibbles Within Accumulator Strt T Start TimerStrt CNT Start Event Counter Xchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data XCH A,R r Exchange Accumulator-Register ContentsXCH A,@R r Exchange Accumulator and Data Memory Contents XRL A,Rr Logical XOR Accumulator With Register Mask XRL A,@R1 Xoracc Contents with Mask LocationXRL A,@Rr Logical XOR Accumulator With Memory Mask XRL A,#data Logical XOR Accumulator With Immediate Mask Appli~ation Examples Page LC Oscillator Mode Crystal Oscillator ModeIntroduction Driving from External Source Application Examples Reset ~~J Rvv-i T1 Multiple Interrupt Sources Ii6 Tf ~r 17&A3 Serves as address latchTt-2 A7 ROM Xtali Both 1/0 and RAM are addressed as data memory =!-39TO F1L This configuration is explained in sectionReset Expander Pinnumbers are Different for ~fd...L DB6 r ~1~ Adding 8 Input Lines ·15 Application Examples Adding Output for KEYBOARD/DISPLAY Scanning RT T T T T JfL Substitute a Application Examples Emulator Circuit DESCRIPTION-6 MHZ Interface to Drum Printer II Keyboard Display TimerRAM Microwave Oven Controller Double Subtract Double ADDDouble Load Double Store Double Left Logical Shift Application Examples Double ExchangeDouble Right Logical Shift Double Right Arithmetic Shift Interrupt Handling Application Examples Binary Multiply R1,A Application Examples Byte Processing SystemCPL Subtract Second from First INC 2sCOMPLEMENT and ADD See AP-49 8 MULTIPLY-ASSEMBLED by MCS-48 Macro Assembler IIn ·1 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-49 APP\,JCATION Examples 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49 Page MCS-4STMComponent Page IIH!T Hmos Single Component 8-BIT Microcomputer Address latch enable. This Used to enable data ontoSignal occurs once during Program store enable. This S04SH/S04SH-1 /S035HL-1/S035H L-1 Absolute Maximum RATINGS· Inter 8048H/8048H-1/8035HL/8035HL.1 BUS Timing AS a Function of TCY Port 2 Timing Waveforms S04SH/S04SH-1/S035HL/S035HL-1Read From External Data Memory 8035HL J3 Xtal Z 8048H/8048H·1/8035HL/8035HL·1 Rll PIN Configuration Logic Symbol Block Diagram Block Diagram PIN Configuration Logic Symbol PIN Description 8048/8035L/8748/8748-6/8748-8/8035/8035-8 AFN-Q1354A-03 Input High Voltage X1, X2, RESEi All Except XTAL1, XTAL2, ResetVOL =2.0 mA Output Low Voltage 10L = 1.8 mA ===i---h·1 Characteristics Port 2 Timing LC Oscillator Mode Crystal Oscillator ModeDriving from External Source PROGRAMMING, VERIFYING, and Erasing the 8748 Eprom TA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ± PROMPT-48 Microcomputer Design Aid, or Waveforms for ProgrammingVerify .I.~---PROGRAM Intel Corporation 108048/8748/8035L 108048/8748/8035L IDS0481S7481S035L Operating CharacteristicsAbsolute Maximum RATINGS· BUSP1, P2BUS, P1, P2 260 TAD Address Setup to Data TAW Address Setup to WRTOR Data Hold PSEN, RD to Data Top Port Control Setup Before Failing Edge of Prog CharacteristicsTpL Port 2 I/O Data Setup TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV Reset Crystal Oscillator Mode Driving from External Source+-----t XTALl Prog TA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ± TA =25C ± 5C, Vee =5V ± 5%, Vee =25V ± PROMPT-48 Microcomputer Design Aid. or Waveforms for Programming Inter Programming Verification Lcoscillator ModeVoo Unit Test Conditions IPHVoo Program Voltage High Level 24.0 2S.0 EA Program or Verify Voltage High Level 21.5 24.5 8748 M8048/M8748/M8035L EA 5 M8048/M8748/M8035L Prog Pin # TpL Port 2 1/0 Data Setup Tcp Port Control Setup Before FallingTpo Output Data Hold Time Tpp Prog Pulae Width TLP Port 2 1/0 Data Hold 120 ALE JI ~----r---I L Characteristics BUS, P1, P2 AN D Operati NG Characteristics Inter 80411803118031 8049/8039 Symbol Parameter Min Max Unit Operating Characteristics ALE JIL --------..1.--1----L Mask Programmable ROM External ROM or Eprom MHz Operation 18049/8039 INr Til IntJ18049/8039 BUS, RD, WR, PSEN, ALE VIH1VOL2 BUS, RD, WR, PSEN, ALE VOH1 Waveforms TAFC--1 I~OATING-I t=t or Port 2 1/0 Data Setup 300 Output Data Setup Time 230TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OV Unit Conditions Note XT AL1 Crystal Oscillator Mode LC Oscillator Mode 8021 PIN Configuration Logic Symbol Block Diagram V1Hl Input High Voltage Xtal 1 & 2, T1 OC to 70CVIH10% Input high voltage all except Xtal 1 T1, RESEl XTAL2 ALE 8022 Prog POO-P07 Reset AvssVTH Varef ANO,AN1 ALE Xtal Fzx 8022 Port 2 Timing IpAL---ooj·1 Analog Input Timing AID Converter Characteristics CNT Analog Input 0, Analog Input TimerMnemonic for in-page Operation Inter GND PIN Description Absolute Maximum Ratings ~~x 125 P20-P23 -- .....--X..... ...Jr 14P52 108243 GND 18243 18243 Tes 1 2 3 4 5 6 7 8 9 10 11 12 # pins= 60 mA-+- 8 mA/pin = 7.5= Output Expander Timing 16,384·8IT ROM with CE1 ResetCE2 Ready 8355/8355-2 Symbol Parameter MIN MAXIII ILO Cl ~ +- Al ~ 8355/8355·2 Input ModeOutput Mode Directly Compatible with SOS5A CPU PIN Configuration Block Diagram PROG/CE1 8755A8755AFUNCTIONAL PIN Definition UPP SA Programming Module Cross Reference Module Name USE withUPPI41 UPP UP2121 8755A Symbol Parameter MIN MAX VILComment Ready Hold Time Prom Read, 1/0 Read and Write Timing Clock Specification for 8755A Wait State Timing Ready =0 Voo Programming Voltage during Write To Eprom Specification ProgrammingITA =OC to 70C Vee =5V ± 5% Vss =OV Program Mode Timing Diagram 8085A 8085A-2 Enable8155-2 8156-2 8155/8156 PIN Functions Timer OUT8155/8156/8155-2/8156-2 8156 Internal Registers Description Reading the Status Register Programming Command Register INPUT/OUTPUT Section Control Input Mode Output ModeBFLowLow INTRLowHigh STB Pca 8155/8156/8155-2/8156-2 Timer Section Example Program WR AD ALE 8085A Minimum System ConfigurationInterval Timer Interrupt Levels Symbol Parameter MIN MAX Units Test Conditions VIL MIN MAX Units Symbol Parameter Write Cycle Read Cycle WI\ J / j 8155/8156/8155-2/8156-2 Basic Output Mode Basic Input Mode PIN Names PIN Configuration Block Diagram 8185/8185-2 Truth Table for Power Down and Function EnableOperational Description Truth Table for Control and Data BUS PIN Status Comment Absolute Maximum Ratings 8185/8185-2 Page Page SINGLE-COMPONENT 8-BIT Microcomputer 8051 Family 0INTRODUCTIONMACRO-VIEW of the 8051 Architecture 8051 CPU Architecture 21/0 Facilities ON-CHIP Peripheral Functions1Interrupt System 8031/8051/8751 8031/8051/8751 3Timer/Event Counters 4Serial Communications 8031/8051/8751 ~=- J~~====~ ~DATA Circuit ground potential 8031/8051/8751 XTAL1 PsenXTAL2 Family Development System and Software Support Universal Prom Programmer Personality Card UPP-851 Symbol Parameter Min Typ Max UnitsWorkshop Insite Library 12MHz Clock Data Memory Write Cycle 8051 Instruction SET Summary Inter8031/8051/8751 All mnemonics copyrlghted@ Intel Corporation InterPage Compatible MCS-48 Components 1024 X 4 BIT Static RAM PIN Configuration 2114A Family Unit Symbol ParameterAddress -..II-------------i--l Normauzed Access Time VS Supply Voltage Typical D.C. and .A.C. Characteristics 2316E 16K 2K 8 ROM 2316E Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI PIN Connection During Read or Program PIN Configuration Operating Characteristics BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10%Family Nco and A.C.OPERATING Conditions During Read 2708·1 limits 2708·6Limits Units Address to Output DelayInput Capacitance VIN = OV Waveforms Family PIN Names PIN Configuration Mode Selection CE = VIH. OE = VIL Programming Cout 2716 Typical 16K Eprom System 2716 Device Operation 2716 8086·2 MPU .. .Zero Wait State ApprovedTwo Line Control Industry Standard Pinout . .. Jedec 8205 Ei==~ fEH2·E3 8205 A13 --..,-H+-q EApplications Eii-+-IH-+t-t r State Decoder Circuit \.. ~ ~ Typical CharacteristicsTA = O·Cto + 75·C, Vee = 5V ± 5% MIN MAX Charactristics Switching CharacteristicsConditions of Test Test Load Test Waveforms IT os PIN Configuration Logic DiagramGD ~s ------- + H DB ---------- -- +i Il D Functional Description+-+1 IE D II. Gated Butter 3-State Basic Schematic SymbolsGated Buffer DS2 , ------,----.J 8212 VI. Output Port With Hand-Shaking Here the 8212 is used as the status latch for an 8080A Bossa AD4 AD5 AD6 AD7 AD2~DI, Stbdo LOW Order CLR Output Currents 100mA 8212Input Load Current, ACK, OS2, CR VF = A5V IOL = 15mA Ili Ffi Typ. Max CIN 051 MD Input Capacitance 9pF 12pF Switching Characteristics052. CK. ACK. DI1-Dls Input Capacitance 5pF DOs Output Capacitance 8pF TCI SGS II,D Icex 821413214 Capacitances 8214/3214 Test Conditions Test Load Circuit Inte 001 ·BITPARALLEL Bidirectional BUS Driver Control aatlng OlEN, CS Bidirectional Driver OUT O---T Waveforms Characteristics Voli VOL2 IFI IF2 IRI IR2 VIL VIH Applications of the 8216/8226 821618226 Octal Latch 8282/8283010 VCC PinD.scrlptlon PIN Definitions Operational Description Tivov VOL VOHTshov Tehoz JJ\~ J/~~ 8282/8283 Vee Intel Bo- B7 Ao-A7 Characteristics for 8286/8287 Jk~ Output Delay vs. Capacitance Output Page Page Synchronous 5·8 Bit Characters Synchronous and Asynchronous Operation Features and Enhancements Iofl CapacitanceCapacitance pF Input Waveforms for AC Tests Bus Parameters !Note MIN MAX Unit Programmable Interval Timer VIIi -.,--.,q General Control Word Register System Interface General Operational DescriptionProgramming Control Word Format 825318253·5 =41 I---t--n --+ Mode 2 Rate Generator MSB 8253/8253-5LSB Mode Register for Latching Count Read Operation ChartRead Operations Reading While Counting Oe to 700 e Input Waveforms for A.C. Tests Bus Parameters NoteRe.dCycle Write Timing Clock and Gate Timing 825318253·5 Programmable Peripheral Interface PIN Configuration 8255A Block Diagram 8255A Functional Description 8255A18255A·58255A Basic Operation Face peripheral devices or structures 8255A18255A·5 PIN Configuration PIN NamesGroup a and Group B Controls Ports A, B, and C 8255A Operational Description Mode SelectionSingle Bit Set/Reset Feature Interrupt Control Functions Operating Modes Mode 0 Configurations Mode 0 Port Definition PA7·pAo 8255AJ8255A·5 II I I I, I0 I0 I0 TPH Input Control Signal DefinitionIBF Input Buffer Full F/F Intr Interrupt Request 10 I ·IOMXlXl Output Control Signal DefinitionIntea Inte B Bidirectional Bus 1/0 Control Signal Definition Combinations of ModeOutput Operations Input Operations LtAOi 8255.Al8255A·5 \, I, erXtJ I0\ ErXtJ I 0\ Only Mode Definition Summary30AFN-00744A-14 Printer Interface Applications of the 8255A MSB PC, r Capacitance MIN. MAX Unit Read CIR TRIT LtR1Bj TwB SIB-Ii SP/EN Programmable Interrupt Controller 8259A Basic Functional Description 8259AInterrupts in Microcomputer Systems Priority Resolver Interrupt Request Register IRR and IN·SERVICE Register ISRInterrupt Mask Register IMR INT Interrupt 8259A Interface to Standard System Bus 8259ACascade BUFFER/COMPARATOR Interrupt Sequence ~O ~ ~ Programming the 8259A Disable FunctionGeneral Input Operation Read Initialization Command Word 3 ICW3 Initialization Command Words 1 and 2 ICW1,ICW2 8259A 0 I 0 I 0 I 0 I 0 lID, liD, lIDo Operation Control Word 1 OCW1 Operation Command Words OCWsOperation Control Word 2 OCW2 Operation Control Words Ocwi Ocwa R,-r-- I-i-Ioo r,-r,-r Operation Command Word FormatOJNTl Buffered Mode Special Mask ModeFully Nested Mode Special Fully Nested Mode Automatic END of Interrupt Aeoi Mode Word enabled onto the data bus during m5 isRotating Priority Mode B Rotation by Software Wol Level Triggered Mode Priority Cell Simplified Logic DiagramThis mode is programmed using bit 3 in ICW1 OH-++-+ 8272 8272 FeaturesRegisters CPU Interface Description 8272 Reset to the Interrupt signal Polling Feature IntJ Command SET Read Data Command Descriptions Transfer Capacity EN End of Cylinder Flag No No Data Flag Write Data Read Deleted Data Write Deleted DataRead a Track Readid Scan Commands Sense Interrupt Status RecalibrateSpecify Sense Drive Status Usa Status Registers BIT Name Symbol Description VIL CLK & WR CLK VIH DC CharacteristicsCINI» VIN=OV ICY ~-----~---V Timing Measurement Conditions Sel-I Block Oiagram LI3 Brief Description of HDLC/SDLC Protocols 8273, 8273·4, 8273·8 Flag DET 32XCLi RAM Programmable KEYBOARD/DISPLAY Interface Principles of Operation 827918279-5Hardware Description 827918279·5 Software Operation Status Word End Interrupt/Error Mode SetData Read Data Write Scanned Keyboard Mode, 2·Key Lockout Interface Considerations ===~ Applications General Block Diagram IIL1 Symbol Test TYP MAXVIL2 BUS Parameters Input Waveforms for A.C. Tests 8279 Display Waveforms Scan Timing Scan Waveforms Gpib TALKER/LISTENER 8291 8291 System DiagramGeneral Purpose Interface BUS Gpib General Description Pacs AcdsAcrs Ppas AH,C SH,AH,T,TE,L,LE,SR,RL,PP,CRemote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DAB DAC DAC Remote Messages Sent ATN DABDAV END DontCare All Write Registers Interrupt Registers SPAS---SPAS Spasc Llcno LLO Lloc Menting this feature, with 80 and Bi enabied from ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi Section on Parallel Poll Protocol Command Pass Through RegisterProvided for Auxiliary Commands Auxiliary Mode Register 2NF Internal CounterAuxiliary Register a Auxiliary Register B Parallel Poll Protocol Reset Procedure 8291 Using DMA 8291 to 8291A Software Compatibility VOH-INT Device Electrical CharacteristicsIlol Iloh Timing Waveforms TwA~ Gpib Timingsii Figure A.1 State Diagrams next Modified State Diagrams 101 TE,L,LE,C,CE Settling Time for Multiline Messages 21stResponse to ATN 200ns Interface Message Accept Time t Appendix C Figure C-l -Wire Handshake Timing at Figure C.2. Handshake Flowchart 105 IIIL---,--11 ,--I 106 Gpib Controller Ai1W Gpib Transceiver BUS1 EOIBUS9 OATA1 =OV Mode 0 PIN DescriptionGpib NDAC* I/O Ieee Gpib NrfoTIL Ndac Mode 1 PIN DescriptionMode 2 PIN Description Ieee Nrfd Mode 3 PIN Description LIEN R1L TiR1 8293 Operating CharacteristicsAbsolute Maximum Ratings Capacitance TA = O·Cto 70·C Vee= 5.0V ± 10% GND = OV CharacteristicsTYP.· MAX ·118 Output Loading Test Circuits Waveforms 8293 8294 ·122 8295 123 ====J UPI·41A Features Enhancements Data Moves Signal DescriptionMnemonic Description Bytes Cycles 8041 Al8641 Al8741 a IU1 VIU Typical 8041/8741A Current Input and Output Waveforms for A.C. TestsRead OPERATION-DATA BUS Buffer Register Write OPERATION-DATA BUS Buffer Register WAVEFORMS-DMA CHARACTERISTICS-PORTCHARACTERISTICS-DMA VOO PROGRAMMING, VERIFYING, and Erasing the 8741A Eprom Vdol Timing Specification for ProgrammingSpecification for Programming 8041Al8641 Al8741A Program Support Products Page Credit Microcomputer Development System 10-2 MODEL225 Functional Description Integral CRT InterMODEL225 System ComponentsPeripheral Interface Control Specifications 110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp Notavailable on bus9800556 9800292Page Intellec Prompt MCS·48 Microcomputer Design AID Single Component Compu.ter Intellec Prompt Features Intellec Prompt Prompt 48 Commands and Functions MCS-48 Processors Intellec Prompt Functional Description Cycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1% User Interrupt causes an Interrupt only IfPrompt system Is running a user program Ordering Information MCS·48 IN·CIRCUIT Emulator ICE·49 ~ L · GO from .START Till XDATA. Rslt Written Memory Mapping ISIS·II ICE·49 EM1 Emulation Board EM1 DC Power Vcc5V ±5% Icc 300 mA max EM1 SpecificationsOrdering Information MDS·EM1 EM2 Emulation Board EM2 40·PIN Socket Configuration EM2 Block DiagramANO AN1 MDS-EM2 EM2UPP-1P3 September Canadian Sales Offices TAvnet Electronics McCormick Avenue Costa Mesa Canadian Distributors IntJ International DISTRIBUTORS/REPRESENTATIVES Bowers Avenue International Sales and Marketing Offices INTEL$ Marketing Offices International Sales and Marketing Offices Canadian Service Offices