Page
MCS-48 Family of Single Chip Microcomputers Usersmanual
September
BXP
Multibus
Credit
Prompt
Table of Contents
Chapters
8051/8751/8031 Microcomputer
Emulation Board
Emulation Board 10-19 UPP-103 Universal Prom Programmer
Insite UsersLibrary
Packing Information
Page
Ntroduction
Page
Introduction to MCS-48
8021 is code compatible but not pin compatible with
Introduction
5.0 and 10.0 J,Lsec Cycle Versions
Eprom
Introduction
Til
Introduction
Function of a Computer
Typical Computer System
Architecture of a CPU
Accumulator
Program Counter Jumps, Subroutines and the Stack
Three levels of subroutines may be ac- commodated
Instruction Register and Decoder
Address Registers
Arithmetic/Logic Unit ALU
Control Circuitry
Computer Operations
Timing
Instruction Fetch
Interrupts
Memory Write
Input/Output
When finished the processor continues on
To the next instructions
Step No. Hex Code Assembly Code MOV RO, #32
Our machine language program then becomes
Step Hex Code
MOV R2, #05
SUB R7
ADD A, # ALFA*BETA/2
Cpla ADD A, REG
Hardware Configuration
Developing An MCS-48 Based Product
Education
Function Definition
Prompt
Intellec Development System
Production
Page
Single Component MCS-4S S~stem
Page
Arithmetic Section
Summary
Architecture
~BUS
Single Component System
Location
Single Component System
Input/Output
Single Component System
R23
Pointer
Jump Conditions
+--1 R
Interrupt Timing
As a Timer
As an Event Counter
Clock and Timing Circuits
Oscillator
ALE --f---+--+
111
Instruction
LOVI
RUN Stop
Power Down Mode
BUS PCO·7
Pin Description
00-07
Designation
Prog
Number Function
Reset
Programming, Verifying and Erasing Eprom
Single Component System
Reset
Test and Debug
Single Step
Disabling Internal Program Memory
Reading Internal Program Memory
Program Memory
Following is a functional description of the major elements
Timer/Event Counter
Oscillator and Clock
Input/Output Capabilities
QUASI-BIDIRECTIONAL Port Structure
Expanded I/O
1 T1 Input
High Current Outputs
Reset
Carry Flag Timer Overflow Flag
10 CPU
Jump Test Condition Instructions Accumulator
Data Memory
Functional Specifications
Program Memory
15Timer/Event Counter
Oscillator and Clock
Port 0 Comparator Inputs
See the 8021 description, .8, for a com- plete explanation
Test and Interrupt Inputs
High Current Outputs
Expanded 1/0
1-3 VAC
Ill
Analog to Digital Converter
19 CPU
Expanded
Page
Summary
Expansion of Program Memory
Expanded MCS-48 System
Interrupt Routines
Latch
AI? Latch
ROM
Expansion of Data Memory
IOW
Expansion of Input/Output
EXPAND!!D MCS-48 System
II AA
Read OO-Port #4 Write Port #5 10 or Port #6 Port #7
Keyboard
RD Display
Expanded MCS-48 System
Expansion Examples See Also Chapter
Multi-Chip MCS-48 Systems
Memory Bank Switching
=====ll 8~~5
Control Signal Summary
Port Characteristics
BUS Port Operations
Port 2 Operations
000
Page
Page
Instruction SET
Instruction SET
Subroutines
Instruction SET
Instruction SET Summary
8021
Instruction SET Summary
RET
PSW
Symbols and Abbreviations Used
DBF
ADD A,R r Add Register Contents to Accumulator
ADD A,@R r Add Data Memory Contents to Accumulator
Addc A,R r Add Carry and Register Contents to Accumulator
ADD A,#data Add Immediate Data to Accumulator
ANL A,@R r Logical and Accumulator With Memory Mask
Addc A,#data Add Carry and Immediate Data to Accumulator
ANL A,R r Logical and Accumulator With Register Mask
Anld Pp,A Logical and Port 4-7 With Accumulator Mask
ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/Y
ANL A,#data Logical and Accumulator With Immediate Mask
Andport 4 Contents
With ACC Bits
MOV RO,#50 Move 50DEC to Address
INC RO Increment REG RET Return to Main Program
10010101111 Contents of the accumulator are cleared to zero
Cpla CPL Aacc Contents are COMPLE- Mented to
11010 Flag 1 is cleared to zero F1-0
11 00 0 Flag 0 is cleared to zero
DA Aacc Adjusted to 00000001 with C SET
AC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001
ADD SIX to Bits
Overflow to C
Example Decrement contents of external data memory location
DEC Rr Decrement Register Not in 8021
EN I Enable External Interrupt
EN Tcnti Enable Timer/Counter Interrupt Not
Ento ClK Enable Clock Output Not in 8021,8022
A,Pp Input Port or Data to Accumulator
INC @R r Increment Data Memory Location
INC a Increment Accumulator
INC Rr Increment Register
IputoPort 0 Data to Accumulator 8021, 8022 Only
INS A,BUS Strobed Iput of BUS Data to Accumulator
JBb address Jump If Accumulator Bit is Set Not in 8021
JC address Jump If Carry Is Set
JF1 address Jump If Flag 1 Is Set Not in 8021
JMP address Direct Jump Within 2K Block
Jmpp @A Indirect Jump Within
JNC address Jump If Carry Is Not Set
JNI address Jump If Interrupt Input is Low Not in 8021
Jnto address Jump If Test 0 Is Low Not
JNT1 address Jump If Test 1 Is Low
JNZ address Jump If Accumulator Is Not Zero
Jump to Timerroutine
IFTF=1
Jump to Location 53 DEC
Jump to Countroutine
MaV A,PSW Move PSW Contents to Accumulator Not in 8021
MaV A,R r Move Register Contents to Accumulator
MaV A,@R r Move Data Memory Contents to Accumulator
Mev A, #data Move Immediate Data to Accumulator
Mev A,T Move Timer/Counter Contents to Accumulator
MaV @Rr,A Move Accumulator Contents to Data Memory
Movp A,@A Move Current Page Data to Accumulator
Movo A,Pp Move Port 4-7 Data to Accumulator
Movo Pp,A Move Accumulator Data to Port
Maxdm Movx A,@R1 Move Contents of Location
MOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022
Not in 8021
Current page are Moved to ACC
NOP The NOP Instruction
ORL A,Rr Logical or Accumulator With Register Mask
ORL A,@Rr Logical or Accumulator With Memory Mask
ORL A,#data Logical OFJ Accumulator With Immediate Mask
8021
Outl Pp,A Output Accumulator Data to Port 1 or
Retr Return With PSW Restore Not in 8021
Rrnc RR Anew ACC Contents are
Example Assume carry is not set and accumulator contains
Rrtc RRC a Carry is SET and ACC
Contains
SEL MBO Select Memory Bank
JMP $+20
Jump to Location
48 HEX
Stop Tcnt Stop Timer/Event-Counter
10110101011
Jump to Routine Intif ACe
BIT 3 is SET REG 7=8
Swap a Swap Nibbles Within Accumulator
Strt T Start Timer
Strt CNT Start Event Counter
Xchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data
XCH A,R r Exchange Accumulator-Register Contents
XCH A,@R r Exchange Accumulator and Data Memory Contents
XRL A,@R1 Xoracc Contents with Mask Location
XRL A,Rr Logical XOR Accumulator With Register Mask
XRL A,@Rr Logical XOR Accumulator With Memory Mask
XRL A,#data Logical XOR Accumulator With Immediate Mask
Appli~ation Examples
Page
Crystal Oscillator Mode
LC Oscillator Mode
Introduction
Driving from External Source
Reset
Application Examples
~~J
Rvv-i T1
Multiple Interrupt Sources
Tf ~r
Ii6
17&A3
Serves as address latch
Tt-2 A7
Xtali
ROM
=!-39TO
Both 1/0 and RAM are addressed as data memory
F1L
This configuration is explained in section
Reset
Expander
~fd...L
Pinnumbers are Different for
~1~
DB6 r
Adding 8 Input Lines
Application Examples
·15
Adding Output for KEYBOARD/DISPLAY Scanning
JfL
RT T T T T
Application Examples Emulator Circuit DESCRIPTION-6 MHZ
Substitute a
Interface to Drum Printer
II Keyboard Display
Timer
RAM
Microwave Oven Controller
Double ADD
Double Subtract
Double Load
Double Store
Application Examples Double Exchange
Double Left Logical Shift
Double Right Logical Shift
Double Right Arithmetic Shift
Application Examples Binary Multiply
Interrupt Handling
Application Examples Byte Processing System
R1,A
CPL Subtract Second from First INC
2sCOMPLEMENT and ADD
8 MULTIPLY-ASSEMBLED by MCS-48 Macro Assembler
See AP-49
IIn ·1
APP\,JCATION Examples
16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-49
16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49
Page
MCS-4STMComponent
Page
Hmos Single Component 8-BIT Microcomputer
IIH!T
Used to enable data onto
Address latch enable. This
Signal occurs once during
Program store enable. This
S04SH/S04SH-1 /S035HL-1/S035H L-1
Inter 8048H/8048H-1/8035HL/8035HL.1
Absolute Maximum RATINGS·
Port 2 Timing
BUS Timing AS a Function of TCY
S04SH/S04SH-1/S035HL/S035HL-1
Waveforms
Read From External Data Memory
8035HL
8048H/8048H·1/8035HL/8035HL·1
J3 Xtal Z
PIN Configuration Logic Symbol Block Diagram
Rll
PIN Configuration Logic Symbol
Block Diagram
8048/8035L/8748/8748-6/8748-8/8035/8035-8
PIN Description
AFN-Q1354A-03
All Except XTAL1, XTAL2, Reset
Input High Voltage X1, X2, RESEi
VOL =2.0 mA
Output Low Voltage 10L = 1.8 mA
===i---h·1
Characteristics Port 2 Timing
Crystal Oscillator Mode
LC Oscillator Mode
Driving from External Source
PROGRAMMING, VERIFYING, and Erasing the 8748 Eprom
TA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ±
PROMPT-48 Microcomputer Design Aid, or
Waveforms for Programming
Verify .I.~---PROGRAM
Intel Corporation
108048/8748/8035L
108048/8748/8035L
Operating Characteristics
IDS0481S7481S035L
Absolute Maximum RATINGS·
BUSP1, P2BUS, P1, P2
TAW Address Setup to WR
260 TAD Address Setup to Data
TOR Data Hold
PSEN, RD to Data
Characteristics
Top Port Control Setup Before Failing Edge of Prog
TpL Port 2 I/O Data Setup
TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV
Crystal Oscillator Mode Driving from External Source
Reset
+-----t XTALl
Prog
TA =25C ± 5C, Vee =5V ± 5%, Vee =25V ±
TA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ±
Waveforms for Programming
PROMPT-48 Microcomputer Design Aid. or
Inter
Programming Verification
Lcoscillator Mode
Voo
IPH
Unit Test Conditions
Voo Program Voltage High Level 24.0 2S.0
EA Program or Verify Voltage High Level 21.5 24.5 8748
EA 5
M8048/M8748/M8035L
M8048/M8748/M8035L
Pin #
Prog
Tcp Port Control Setup Before Falling
TpL Port 2 1/0 Data Setup
Tpo Output Data Hold Time Tpp Prog Pulae Width
TLP Port 2 1/0 Data Hold 120
Characteristics
ALE JI ~----r---I L
AN D Operati NG Characteristics
BUS, P1, P2
Inter
80411803118031
8049/8039
Operating Characteristics
Symbol Parameter Min Max Unit
ALE JIL --------..1.--1----L
18049/8039
Mask Programmable ROM External ROM or Eprom MHz Operation
INr
IntJ18049/8039
Til
VIH1
BUS, RD, WR, PSEN, ALE
VOL2
BUS, RD, WR, PSEN, ALE VOH1
TAFC--1 I~OATING-I t=t or
Waveforms
Output Data Setup Time 230
Port 2 1/0 Data Setup 300
TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OV
Unit Conditions Note
Crystal Oscillator Mode LC Oscillator Mode
XT AL1
PIN Configuration Logic Symbol Block Diagram
8021
OC to 70C
V1Hl Input High Voltage Xtal 1 & 2, T1
VIH10% Input high voltage all except Xtal 1
T1, RESEl
ALE
XTAL2
8022
Reset Avss
Prog POO-P07
VTH
Varef ANO,AN1 ALE Xtal
8022
Fzx
IpAL---ooj·1
Port 2 Timing
AID Converter Characteristics
Analog Input Timing
CNT
Analog Input 0, Analog Input Timer
Mnemonic for in-page Operation
Inter
PIN Description
GND
Absolute Maximum Ratings
~~x
125
P20-P23 -- .....--X..... ...Jr
108243
14P52
18243
GND
18243
Tes
# pins= 60 mA-+- 8 mA/pin = 7.5=
1 2 3 4 5 6 7 8 9 10 11 12
Output Expander Timing
16,384·8IT ROM with
Reset
CE1
CE2
Ready
Symbol Parameter MIN MAX
8355/8355-2
III
ILO
+- Al ~
Cl ~
8355/8355·2
Input Mode
Output Mode
PIN Configuration Block Diagram
Directly Compatible with SOS5A CPU
PROG/CE1
8755A
8755AFUNCTIONAL PIN Definition
SA Programming Module Cross Reference Module Name USE with
UPP
UPPI41
UPP UP2121
Symbol Parameter MIN MAX VIL
8755A
Comment
Ready Hold Time
Clock Specification for 8755A
Prom Read, 1/0 Read and Write Timing
Wait State Timing Ready =0
Voo Programming Voltage during Write To Eprom
Specification Programming
ITA =OC to 70C Vee =5V ± 5% Vss =OV
Program Mode Timing Diagram
Enable
8085A 8085A-2
8155-2
8156-2
8155/8156 PIN Functions
Timer OUT
8155/8156/8155-2/8156-2
Description
8156 Internal Registers
Programming Command Register
Reading the Status Register
Control Input Mode Output Mode
INPUT/OUTPUT Section
BFLowLow INTRLowHigh
STB
8155/8156/8155-2/8156-2
Pca
Timer Section
Example Program
WR AD ALE
8085A Minimum System Configuration
Interval Timer Interrupt Levels
Symbol Parameter MIN MAX Units Test Conditions VIL
Symbol Parameter
MIN MAX Units
Read Cycle
Write Cycle
8155/8156/8155-2/8156-2
WI\ J / j
Basic Input Mode
Basic Output Mode
PIN Configuration Block Diagram
PIN Names
Truth Table for Power Down and Function Enable
8185/8185-2
Operational Description
Truth Table for Control and Data BUS PIN Status
Absolute Maximum Ratings
Comment
8185/8185-2
Page
Page
SINGLE-COMPONENT 8-BIT Microcomputer
0INTRODUCTION
8051 Family
MACRO-VIEW of the 8051 Architecture
8051 CPU Architecture
21/0 Facilities
ON-CHIP Peripheral Functions
1Interrupt System
8031/8051/8751
3Timer/Event Counters
8031/8051/8751
8031/8051/8751
4Serial Communications
~=- J~~====~
~DATA
8031/8051/8751
Circuit ground potential
Psen
XTAL1
XTAL2
Family Development System and Software Support
Symbol Parameter Min Typ Max Units
Universal Prom Programmer Personality Card UPP-851
Workshop
Insite Library
12MHz Clock
Data Memory Write Cycle
Inter8031/8051/8751
8051 Instruction SET Summary
Inter
All mnemonics copyrlghted@ Intel Corporation
Page
Compatible MCS-48 Components
PIN Configuration
1024 X 4 BIT Static RAM
2114A Family
Unit
Symbol Parameter
Address -..II-------------i--l
Typical D.C. and .A.C. Characteristics
Normauzed Access Time VS Supply Voltage
2316E 16K 2K 8 ROM
2316E
Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI
PIN Configuration
PIN Connection During Read or Program
BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10%
Operating Characteristics
Family
Nco and A.C.OPERATING Conditions During Read
Address to Output Delay
2708·1 limits 2708·6Limits Units
Input Capacitance
VIN = OV
Family
Waveforms
PIN Configuration Mode Selection
PIN Names
Programming
CE = VIH. OE = VIL
2716
Cout
2716
Typical 16K Eprom System
2716
Device Operation
Approved
8086·2 MPU .. .Zero Wait State
Two Line Control
Industry Standard Pinout . .. Jedec
8205
Ei==~ fEH2·E3
A13 --..,-H+-q E
8205
Applications
Eii-+-IH-+t-t r
State Decoder Circuit
Typical Characteristics
\.. ~ ~
TA = O·Cto + 75·C, Vee = 5V ± 5%
MIN MAX
Switching Characteristics
Charactristics
Conditions of Test Test Load
Test Waveforms
PIN Configuration Logic Diagram
IT os
GD ~s ------- + H
DB ---------- -- +i
Functional Description
Il D
+-+1
IE D
Basic Schematic Symbols
II. Gated Butter 3-State
Gated Buffer
DS2 , ------,----.J
8212
Here the 8212 is used as the status latch for an 8080A
VI. Output Port With Hand-Shaking
AD2
Bossa AD4 AD5 AD6 AD7
~DI, Stbdo LOW Order
CLR
8212
Output Currents 100mA
Input Load Current, ACK, OS2, CR VF = A5V
IOL = 15mA
Ffi
Ili
Switching Characteristics
Typ. Max CIN 051 MD Input Capacitance 9pF 12pF
052. CK. ACK. DI1-Dls Input Capacitance 5pF
DOs Output Capacitance 8pF
TCI
II,D
SGS
821413214
Icex
8214/3214
Capacitances
Inte
Test Conditions Test Load Circuit
·BITPARALLEL Bidirectional BUS Driver
001
Bidirectional Driver
Control aatlng OlEN, CS
Waveforms Characteristics
OUT O---T
IFI IF2 IRI IR2 VIL VIH
Voli VOL2
821618226
Applications of the 8216/8226
8282/8283
Octal Latch
010
VCC
PIN Definitions Operational Description
PinD.scrlptlon
VOL VOH
Tivov
Tshov
Tehoz
JJ\~ J/~~
8282/8283
Intel
Vee
Ao-A7
Bo- B7
Characteristics for 8286/8287
Output Delay vs. Capacitance
Jk~
Output
Page
Page
Synchronous and Asynchronous Operation
Synchronous 5·8 Bit Characters
Features and Enhancements
Iofl
Capacitance
Capacitance pF
Bus Parameters !Note
Input Waveforms for AC Tests
MIN MAX Unit
Programmable Interval Timer
General
VIIi -.,--.,q
System Interface
Control Word Register
Operational Description
General
Programming
Control Word Format
825318253·5
Mode 2 Rate Generator
=41 I---t--n --+
MSB
8253/8253-5
LSB
Read Operation Chart
Mode Register for Latching Count
Read Operations
Reading While Counting
Oe to 700 e
Bus Parameters Note
Input Waveforms for A.C. Tests
Re.dCycle
Write Timing
825318253·5
Clock and Gate Timing
PIN Configuration 8255A Block Diagram
Programmable Peripheral Interface
8255A18255A·5
8255A Functional Description
8255A Basic Operation
Face peripheral devices or structures
PIN Configuration PIN Names
8255A18255A·5
Group a and Group B Controls
Ports A, B, and C
8255A Operational Description
Mode Selection
Single Bit Set/Reset Feature
Operating Modes
Interrupt Control Functions
Mode 0 Port Definition
Mode 0 Configurations
8255AJ8255A·5
PA7·pAo
II I I I, I0 I0 I0
Input Control Signal Definition
TPH
IBF Input Buffer Full F/F
Intr Interrupt Request
Output Control Signal Definition
10 I ·IOMXlXl
Intea
Inte B
Combinations of Mode
Bidirectional Bus 1/0 Control Signal Definition
Output Operations
Input Operations
8255.Al8255A·5
LtAOi
ErXtJ I 0\
\, I, erXtJ I0\
Only
Mode Definition Summary
30AFN-00744A-14
Applications of the 8255A
Printer Interface
PC, r
MSB
Capacitance
Read
MIN. MAX Unit
CIR
TwB
TRIT LtR1Bj
SIB-Ii
Programmable Interrupt Controller
SP/EN
8259A Basic Functional Description
8259A
Interrupts in Microcomputer Systems
Interrupt Request Register IRR and IN·SERVICE Register ISR
Priority Resolver
Interrupt Mask Register IMR
INT Interrupt
8259A
8259A Interface to Standard System Bus
Cascade BUFFER/COMPARATOR
Interrupt Sequence
~O ~ ~
Disable Function
Programming the 8259A
General
Input Operation Read
Initialization Command Words 1 and 2 ICW1,ICW2
Initialization Command Word 3 ICW3
0 I 0 I 0 I 0 I 0 lID, liD, lIDo
8259A
Operation Command Words OCWs
Operation Control Word 1 OCW1
Operation Control Word 2 OCW2 Operation Control Words Ocwi
Ocwa
R,-r-- I-i-Ioo r,-r,-r
Operation Command Word Format
OJNTl
Special Mask Mode
Buffered Mode
Fully Nested Mode
Special Fully Nested Mode
Word enabled onto the data bus during m5 is
Automatic END of Interrupt Aeoi Mode
Rotating Priority Mode B Rotation by Software
Wol
Priority Cell Simplified Logic Diagram
Level Triggered Mode
This mode is programmed using bit 3 in ICW1
OH-++-+
8272
Features
8272
Registers CPU Interface
Description
8272
Polling Feature
Reset to the Interrupt signal
IntJ
Command SET
Command Descriptions
Read Data
Write Data
Transfer Capacity EN End of Cylinder Flag No No Data Flag
Write Deleted Data
Read Deleted Data
Read a Track
Readid
Scan Commands
Recalibrate
Sense Interrupt Status
Specify
Sense Drive Status
Status Registers BIT Name Symbol Description
Usa
DC Characteristics
VIL CLK & WR CLK VIH
CINI»
VIN=OV
ICY
~-----~---V
Sel-I
Timing Measurement Conditions
LI3
Block Oiagram
8273, 8273·4, 8273·8
Brief Description of HDLC/SDLC Protocols
32XCLi
Flag DET
Programmable KEYBOARD/DISPLAY Interface
RAM
Principles of Operation
827918279-5
Hardware Description
827918279·5
Software Operation
End Interrupt/Error Mode Set
Status Word
Data Read
Data Write
Interface Considerations
Scanned Keyboard Mode, 2·Key Lockout
===~
General Block Diagram
Applications
IIL1
Symbol Test TYP MAX
VIL2
Input Waveforms for A.C. Tests
BUS Parameters
8279
Scan Timing Scan Waveforms
Display Waveforms
Gpib TALKER/LISTENER
8291
System Diagram
8291
General Purpose Interface BUS Gpib
General Description
Acds
Pacs
Acrs
Ppas
SH,AH,T,TE,L,LE,SR,RL,PP,C
AH,C
Remote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DAB
DAC
Remote Messages Sent ATN DAB
DAC
DAV
END
All Write Registers
DontCare
SPAS---SPAS Spasc Llcno LLO Lloc
Interrupt Registers
Menting this feature, with 80 and Bi enabied from
ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi
Section on Parallel Poll Protocol
Command Pass Through Register
Provided for
Auxiliary Mode Register
Auxiliary Commands
Internal Counter
2NF
Auxiliary Register a
Auxiliary Register B
Reset Procedure
Parallel Poll Protocol
8291 Using DMA 8291 to 8291A Software Compatibility
Device Electrical Characteristics
VOH-INT
Ilol
Iloh
TwA~
Timing Waveforms
Gpib Timingsii
Modified State Diagrams
Figure A.1 State Diagrams next
101
TE,L,LE,C,CE
Settling Time for Multiline Messages 21st
Response to ATN 200ns Interface Message Accept Time t
Figure C-l -Wire Handshake Timing at
Appendix C
Figure C.2. Handshake Flowchart
IIIL---,--11 ,--I
105
Gpib Controller
106
Ai1W
Gpib Transceiver
EOI
BUS1
BUS9
OATA1
Mode 0 PIN Description
=OV
Gpib
NDAC* I/O
Ieee Gpib
Nrfo
TIL
Ndac
Mode 1 PIN Description
Mode 2 PIN Description
Nrfd
Ieee
Mode 3 PIN Description
R1L
LIEN
TiR1
Operating Characteristics
8293
Absolute Maximum Ratings
Capacitance
Characteristics
TA = O·Cto 70·C Vee= 5.0V ± 10% GND = OV
TYP.· MAX
·118
Output Loading Test Circuits
8293
Waveforms
8294
8295
·122
====J
123
UPI·41A Features Enhancements
Data Moves
Signal Description
Mnemonic Description Bytes Cycles
8041 Al8641 Al8741 a
VIU
IU1
Input and Output Waveforms for A.C. Tests
Typical 8041/8741A Current
Read OPERATION-DATA BUS Buffer Register
Write OPERATION-DATA BUS Buffer Register
WAVEFORMS-DMA
CHARACTERISTICS-PORT
CHARACTERISTICS-DMA
PROGRAMMING, VERIFYING, and Erasing the 8741A Eprom
VOO
Vdol
Timing Specification for Programming
Specification for Programming
Program
8041Al8641 Al8741A
Support Products
Page
Microcomputer Development System
Credit
MODEL225 Functional Description
10-2
InterMODEL225 System Components
Integral CRT
Peripheral Interface
Control
Specifications
Notavailable on bus
110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp
9800556
9800292
Page
Intellec Prompt MCS·48 Microcomputer Design AID
Intellec Prompt Features
Single Component Compu.ter
Prompt 48 Commands and Functions
Intellec Prompt
Intellec Prompt Functional Description
MCS-48 Processors
Cycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1%
User Interrupt causes an Interrupt only If
Prompt system Is running a user program
Ordering Information
MCS·48 IN·CIRCUIT Emulator
~ L ·
ICE·49
Memory Mapping
GO from .START Till XDATA. Rslt Written
ICE·49
ISIS·II
EM1 Emulation Board
EM1
EM1 Specifications
DC Power Vcc5V ±5% Icc 300 mA max
Ordering Information
MDS·EM1
EM2 Emulation Board
40·PIN Socket Configuration EM2 Block Diagram
EM2
ANO
AN1
MDS-EM2
EM2
UPP-1P3
Canadian Sales Offices
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International Sales and Marketing Offices
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Canadian Service Offices
