Intel mcs-48 manual 825318253·5, Clock and Gate Timing

825318253·5

Clock and Gate Timing:

		8253			8253-5
SYMBOL	PARAMETER	MIN.	MAX.	MIN.	MAX.	UNIT
tCLK	Clock Per iod	380	de	380	de	ns
tPWH	High Pulse Width	230		230		ns
tPWL	Low Pulse Width	150		150		ns
tGW	Gate Width High	150		150		ns
tGL	Gate Width Low	100		100		ns
tGS	Gate Set Up Time to CLKt	100		100		ns
tGH	Gate Hold Time After CLKt	50		50		ns
too	Output Delay From CLK~111		400		400	ns
tOOG	Output Delay From Gate~111		300		300	ns

Note 1: Test Conditions: 8253: CL = 1OOpF; 8253·5: CL = 150pF.

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9-16AFN-007~A-ll