Intel mcs-48 8185/8185-2, Operational Description, Truth Table for Power Down and Function Enable

8185/8185-2

OPERATIONAL DESCRIPTION

The 8185 has been designed to provide for direct interface to the multiplexed bus structure and bus timing of the 8085A microprocessor.

At the beginning of an 8185 memory access cycle, the 8- bit address on ADo-7, As and Ag, and the status of CEI and CE2 are all latched internally in the 8185 by the falling edge of ALE. If the latched status of both CEI and CE2 are active, the 8185 powers itself up, but no action occurs until the CS line goes low and the appropriate RD or WR control signal input is activated.

The CS input is not latched by the 8185 in order to allow the maximum amount of time for address decoding in selecting the 8185 chip. Maximum power consumption savings will occur, however, only when CEI and CE2 are activated selectively to power down the 8185 when it is not in use. A possible connection would be to wirethe 8085A's 101M line to the 8185'sCEI input, thereby keeping the 8185 powered down during 1/0 and interrupt cycles.

TABLE 1.

TRUTH TABLE FOR

POWER DOWN AND FUNCTION ENABLE

CE1 CE2 CS			{CS*)[2]	8185 Status
1	X	X	0	Power Down and
				Function Disablell]
X	0	X	0	Power Down and
				Function Disable[l]
0	1	1	0	Powered Up and
				Function Disable[l]
0	1	0	1	Powered Up and
				Enabled

Notes:

X: Don'tCare.

1:Function Disable implies Data Bus in high impedance state and not writing.

2:CS'= (CEI = 0) • (CE2 = 1) • (CS = 0)

CS· = 1 signifies all chip enables and chip select active

TABLE 2.

TRUTH TABLE FOR

CONTROL AND DATA BUS PIN STATUS

ADo_7 During Data

(CS*) RD WR Portion of Cycle 8185 Function

0X X Hi-Impedance No Function

10 1 Data from Memory Read

1 1 0 Data to Memory Write

11 1 Hi-Impedance Reading, but not Driving Data Bus

Note:

X: Don'tCare.

-		r1D~ VssI		VeeI I
	TRAP	X,	X,	RESET IN
				HOLD
	RST7,5			HLDA
	AST6,S			SOD '--
- RST5,5			8085A	SID	--
-	INTR			9,	-r--
-	1NTA			RESET
		ADDRi		OUT 90 -
-	ADDR	DATA	ALE Ali WIi 101M ROY eLK			T
	,81	,81			VI'
	H-				~	POR~~
					WR	PORT ~(8)
					R0 8156 B
					ALE	'ORTP(>
					DATAl	c	(6)
		"			ADDR
						IN
					101MRESET TIMEROUT ~
					lOW
	Il-r-				Ali		p(>
					CE
					ALE	PORT
	~~					A
				V	8355/
				"-	As.10
					8755A
					DATAl
					ADDR		p(>
					RESET
					101M	PORT
						8
					ROV
				~ eLK
					vs! v!c V~DtROG
					WR
					RO
					CE, 8185
					ALE
	H--				es, CE 2
	H--				As, Ag
					ADQ.7
					vL	vL

Vee

Vee

Figure 1. 8185 in an MCS-85 System.

4 Chips:

2K Bytes ROM

1.25K Bytes RAM

38 I/O Lines

1Counter/Timer

2Serial I/O Lines

5Interrupt Inputs

6-97 AFN-00201 A-02