Intel mcs-48 manual Programmable Interrupt Controller, Sp/En

8259A

PROGRAMMABLE INTERRUPT CONTROLLER

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•

MCS·86™ Compatible	• Programmable Interrupt Modes
MCS·80185™ Compatible	• Individual Request Mask Capability

•	Elght·Level Priority Controller	•	Single + 5V Supply (No Clocks)
•	Expandable to 64 Levels	•	28·Pin Dual·ln·Line Package

The Intell!l 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses

NMOS technology and requires a single + 5V supp!y_ Circuitry is static, requiring no clock input.

The 8259A is designed to minimize the software and real time overhead in handling mUlti-level priority interrupts_ It has several modes, permitting optimization for a variety of system requirements.

The 8259A is fully upward compatible with the Intel<i> 8259. Software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).

	PIN CONFIGURATION				BLOCK DIAGRAM
	CS			vee	INTA	INT
	iVA			Au
	AD			INTA
	0,			IR7
	0,			IRG	DATA
	Os			IR5	BUS
					BUFFER
	0,			IR4
	0,			IR3
	0,			IR2
	D,			IRI
	0,			IRO		-IRO
				INT
	CASO				WR-	-IR1
	CASI			SP/EN
	GND			CAS2
		PIN NAMES			cs -
D7·~.~L		DATA BUS IBI-DIRECTIONALI
AD		READ INPUT	._".
iVA		WRITE INPUT
					CAS1 _
Ao		COMMAND SELECT ADDRESS
cs		CHIP SELECT			CAS2 ... --
CAS2-CASO		CASCADE LINES		_________ _
!lI'/£I'J		SLAVE PROGRAM INPUT/ENABLE			'INTERNALBUS
INT	__ 'NT~!l.uPT OU!!.l!!.____
		INTERRUPT ACKNOWLEDGE INPUT
IRO-IR7		INTERRUPT REaUEST INPUTS

INTEL CORPORAmlN ASSUMES NO RESPONSIBILITY FOR THE US[ Of ANY CIRCUITRY OTHER THAN CIRCUITRY EIIIIOOlEO IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPlIEO.

" INTEL CORPORATION. 1979

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