Intel mcs-48 manual 8272, Registers CPU Interface, Description, Features, Function

8272

8272 SYSTEM BLOCK DIAGRAM 8272 REGISTERS CPU INTERFACE

8237	i5ACK	8272
DMA
		FDC
CONTROLLER
L -__--I	TC
	TERMINAL L....__.J

COUNT

DESCRIPTION

Hand-shaking signals are provided in the 8272 which make DMA operation easy to incorporate with the aid of an external DMA Controller chip, such as the 8237. The FDC will operate in either DMA or Non-DMA mode. In the Non-DMA mode, the FDC generates interrupts to the processor for every transfer of a data byte between the CPU and the 8272. In the DMA mode, the processor need only load a command into the FDC and all data transfers

The 8272 contains two registers which may be accessed by the main system processor; a Status Register and a Data Register, The 8-bit Main Status Register contains the status information of the FDC, and may be accessed at any time. The 8-bit Data Register (actually consists of several registers in a stack with only one register pre- sented to the data·bus at a time), stores data, com- mands, parameters, and FDD status information. Data bytes are read out of, or written into, the Data Register in order to program or obtain the results after execution of a command. The Status Register may only be read and is used to facilitate the transfer of data between the processor and 8272.

The relationship between the Status/Data registers and the signals RD, WR, and Ao is shown below.

Ao	RD	WR	FUNCTION
0	0	i	Head Main l::itatus
			Register
0	1	0	Illegal
0	0	0	Illegal
1	0	0	Illegal
1	0	1	Read from Data Register
1	1	0	Write into Data Register

The bits in the Main Status Register are defined as follows:

occur under control of the 8272 and DMA controller.

There are 15 separate commands which the 8272 will execute. Each of these commands require multiple 8-bit bytes to fully specify the operation which the processor wishes the FDC to perform. The following commands are available.

BIT NUMBER	NAME	SYMBOL
080	FOO 0 Busy	008
08,	FDD 1 Busy	0,8
082	FDD 2 Busy	028

DESCRIPTION

FOO numberO is in the Seek mode.

FOO number 1 is in the Seek mode.

FOD number2 is in the Seek mode.

Read Data Read ID

Read Deleted Data Read a Track Scan Equal

Scan High or Equal Scan Low or Equal Specify

Write Data

Format a Track

Write Deleted Data

Seek

Recalibrate (Restore to

Track 0)

Sense Interrupt Status

Sense Drive Status

083	FOD 3 Busy	038
084	FOC Busy	C8
085	Non·DMAmode	NOM

FDO number3 is in the Seek mode.

A read or write command is in process.

The FOe is in the non·DMA mode. This bit is set only during the execution phase in non·DMAmode. Tran-

sition to "0" state indicates

execution phase has ended.

FEATURES

Address mark detection circuitry is internal to the FDC which simplifies the phase locked loop and read elec- tronics. The track stepping rate, head load time, and head unload time may be programmed by the user. The 8272 offers many additional features such as multiple sector transfers in both read and write modes with a single command, and full IBM compatibility in both single (FM) and double density (MFM) modes.

086	Data Input/Output	010
087	Request for	ROM
	Master

Indicates direction of data transfer between FOe and Data Register. If 010="1" then transfer Is from Data Register to the Processor. If 010 = "0", then_ transfer is -from the Processor to Data Register.

Indicates Data Register is ready to send or receive data to or from the Proc· essor. Both bits 010 and ROM should be used to perform the handshaking functions of "ready" and "direction" to the processor.

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